TITLE:
System-on-Chip Test Data Compression Based on Split-Data Variable Length (SDV) Code
AUTHORS:
J. Robert Theivadas, V. Ranganathan, J. Raja Paul Perinbam
KEYWORDS:
Test Data Compression, SDV Codes, SOC, ATE, Benchmark Circuits
JOURNAL NAME:
Circuits and Systems,
Vol.7 No.8,
June
6,
2016
ABSTRACT: System-on-a-chips with
intellectual property cores need a large volume of data for testing. The large
volume of test data requires a large testing time and test data memory.
Therefore new techniques are needed to optimize the test data volume, decrease
the testing time, and conquer the ATE memory limitation for SOC designs. This
paper presents a new compression method of testing for intellectual property
core-based system-on-chip. The proposed method is based on new split- data
variable length (SDV) codes that are designed using the split-options along
with identification bits in a string of test data. This paper analyses the
reduction of test data volume, testing time, run time, size of memory required
in ATE and improvement of compression ratio. Experimental results for ISCAS 85
and ISCAS 89 Benchmark circuits show that SDV codes outperform other
compression methods with the best compression ratio for test data compression.
The decompression architecture for SDV codes is also presented for decoding the
implementations of compressed bits. The proposed scheme shows that SDV codes
are accessible to any of the variations in the input test data stream.