B. Shirazi, D. Yun and C. Zhang, “VLSI Designs for redundant Binary-Coded Decimal Addition,” 7th Annual International Phoenix Conference on Computers and Communications, Scottsdale, 16-18 March 1988, pp. 52-56. doi:10.1109/PCCC.1988.10042

has been cited by the following article:

• TITLE: Fast Signed-Digit Multi-operand Decimal Adders

  AUTHORS: Jeff Rebacz, Erdal Oruklu, Jafar Saniie

  KEYWORDS: Computer Arithmetic, Decimal Arithmetic, Signed-Digit, Multi-operand Adder, BCD

  JOURNAL NAME: Circuits and Systems, Vol.2 No.3, July 20, 2011

  ABSTRACT: Decimal arithmetic is desirable for high precision requirements of many financial, industrial and scientific applications. Furthermore, hardware support for decimal arithmetic has gained momentum with IEEE 754-2008, which standardized decimal floating-point. This paper presents a new architecture for two operand and multi-operand signed-digit decimal addition. Signed-digit architectures are advantageous because there are no carry-propagate chains. The proposed signed-digit adder reduces the critical path delay by parallelizing the correction stage inherent to decimal addition. For performance evaluation, we synthesize and compare multiple unsigned and signed-digit multi-operand decimal adder architectures on 0.18μm CMOS VLSI technology. Synthesis results for 2, 4, 8, and 16 operands with 8 decimal digits provide critical data in determining each adder's performance and scalability.