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**Fast Signed-Digit Multi-operand Decimal Adders** ()

Decimal arithmetic is desirable for high precision requirements of many financial, industrial and scientific applications. Furthermore, hardware support for decimal arithmetic has gained momentum with IEEE 754-2008, which standardized decimal floating-point. This paper presents a new architecture for two operand and multi-operand signed-digit decimal addition. Signed-digit architectures are advantageous because there are no carry-propagate chains. The proposed signed-digit adder reduces the critical path delay by parallelizing the correction stage inherent to decimal addition. For performance evaluation, we synthesize and compare multiple unsigned and signed-digit multi-operand decimal adder architectures on 0.18μm CMOS VLSI technology. Synthesis results for 2, 4, 8, and 16 operands with 8 decimal digits provide critical data in determining each adder's performance and scalability.

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J. Rebacz, E. Oruklu and J. Saniie, "Fast Signed-Digit Multi-operand Decimal Adders,"

*Circuits and Systems*, Vol. 2 No. 3, 2011, pp. 225-236. doi: 10.4236/cs.2011.23032.Conflicts of Interest

The authors declare no conflicts of interest.

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