A Simple On-Chip Automatic Tuning Circuit for Continuous-Time Filter

Chia-Hsiung KAO, Ping-Yu TSAI, I-Fan CHANG

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DOI: 10.4236/ijcns.2010.31009                

Abstract

A simple on-chip automatic frequency tuning circuit is proposed. The tuning circuit is modified from voltage-controlled filter (VCF) frequency tuning circuit. We utilize an operational transconductance amplifier and a capacitor to from a single-time constant (STC) circuit which can produce a controllable delay time clock to tune the frequency of the filter. It can efficiently reduce the deviations in the 3 dB bandwidth from the variations of PVT (Process, Voltage and Temperature). The design of the STC circuit is simpler than VCF and it has less chip area. The chip has been implanted using TCMC 0.35 μm CMOS technology and the power consumption is less than 9.05 mW.

Keywords

Automatic, Tuning, Voltage-Controlled Filter (VCF), Single-Time Constant (STC)

A simple on-chip automatic frequency tuning circuit is proposed. The tuning circuit is modified from voltage-controlled filter (VCF) frequency tuning circuit. We utilize an operational transconductance amplifier and a capacitor to from a single-time constant (STC) circuit which can produce a controllable delay time clock to tune the frequency of the filter. It can efficiently reduce the deviations in the 3 dB bandwidth from the variations of PVT (Process, Voltage and Temperature). The design of the STC circuit is simpler than VCF and it has less chip area. The chip has been implanted using TCMC 0.35 μm CMOS technology and the power consumption is less than 9.05 mW.

1. Introduction

Analog continuous-time filters [1] are popular in various application, such as video and audio signal processing, ADC, mobile phone, hard disk reading channels, CDROM, etc. Recently, the Gm-C filters are widely used in the CMOS technology. The Gm-C filters have higher frequency and flexibility than other analog filter types. However, their performances vary with process and environment variations. The frequency response of analog continuous-time filters is determined by resistors, capacitors or transconductors. However, the process variation, temperature drift and aging, make the integrated RC time constants vary about 30% [2,3]. At extreme conditions, the maximum frequency response deviations could be up to 50% [4]. To achieve the desired filter performance, an on-chip automatic tuning scheme is usually required [5–14].

Many kinds of frequency automatic-tuning methods are derived from phase locked loop (PLL) for analog filters, such as sinusoidal oscillator based PLL tuning circuit, voltage-controlled filter (VCF) tuning circuit and etc [1,5,6,13]. The drawbacks of the sinusoidal oscillator based PLL tuning are large size and hard to design. As to the voltage-controlled filter tuning circuit, the power consumption is high and the reference clock needs to be a pure sine wave. According to the aforementioned, we try to make the tuning circuit have following advantages: simplicity, small chip area, good matching with the filter and less power consumption.

In the following sections, Section 2 presents the proposed tuning circuit and the Gm-C filter and the experimental results are discussed in Section 3. Section 4 summarizes the conclusions of this paper.

2. The Proposed Tuning Circuit and the Gm-C Filter

2.1. The Operation of Proposed Tuning Mechanism

Figure 1 shows the proposed tuning circuit scheme. Firstly, the frequency tuning circuit is modified from voltage-controlled filter (VCF) frequency tuning circuit. We replace VCF by a single-time-constant (STC) circuit and the input signal could be square wave. The function of STC is to produce a delay clock which the delay can be controlled. The phase difference will make the charge pump (CP) produce a control voltage. The phase difference is 45° between the reference clock and the output of the voltage comparator. The tuning circuit depends on the constant phase difference to tune the slave filter. Finally, it generates the control voltage after the voltage signal is filtered by the low pass filter (LPF).

Next, we discuss the STC circuit. The STC circuit consists of a tunable OTA, as shown in Figure 2, and a capacitor. We use the tunable OTA to simulate a variable resistance, and we obtain a STC circuit by connecting the OTA with a capacitor.

Figure 1. The block diagram of tuning circuit. (PD: Phase Detector, CP: Charge Pump, LPF: Low Pass Filter).

Figure 2. The STC circuit.

Figure 3. (A) Reference clock (B) STC output wave with three different Vc.

Figure 4. (A) Reference clock (B) The output of the STC circuit (C) The output of the voltage comparator (D) The output of the PD.

The transfer function of the STC is

(1)

(2)

If we input a reference clock, the STC will output a pseudo-triangular wave. The output wave of the STC circuit with three different control voltages V_c are shown in Figure 3.

When we input a reference clock with amplitude ± V_D as shown in Figure 4(A), the STC circuit will output a pseudo-triangular wave with amplitude ± V_a as shown in Figure 4(B). The pseudo-triangular wave is symmetrical with respect to the zero voltage. We will use a voltage comparator which is referenced at the zero voltage, so it will produce a clock with a delay time, t', as shown in Figure 4(C). We can find out the relation between the delay time and the time constant, τ, of the pseudo-triangular wave.

From Figure 4(B), it can be derived that the relation between t' and τ is:

(3)

(4)

Figure 5. t'/T VS T/τ.

   

Figure 6. Charge and discharge current.

Figure 7. The structure of proposed tuning circuit ((1): STC circuit, (2): Voltage comparator, (3): Phase Detector, (4): Charge Pump, (5): Low Pass Filter).

Figure 5 is the curve of Equation (3). If we choose t'/T = 1/8, then α = 0.776. When T = 10MHz, the critical frequency of the STC is 7.76MHz.

Conflicts of Interest

The authors declare no conflicts of interest.

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