Reconfigurable Digital Circuits Based on Chip Expander with Integrated Temperature Regulation


This article is dealing with a development of custom chip expander platform with the possibility of accurate temperature control and integration of additional silicon-based features. Such platform may serve as a useful tool which facilitates the burdens connected with measurement and analysis tasks of experimental semiconductor structures. The devised solution provides the functionality of carrier substrate (Al2O3 compound) with CTE compatibility to the experimental silicon chip and is fully customizable with respect to a particular chip. It also allows achieving an easy fan-out of small-diameter chip terminals into a larger, more convenient area and placement of chip specimens conveniently into space-constrained chamber of the AFM microscopes, probe stations, etc. Real application of the developed chip expander platform is demonstrated in context of digital reconfigurable circuits based on polymorphic electronics. In this case the chip expander with attached polymorphic chip REPOMO is thermally stabilized at an ambient temperature level up to approximately 135C and its sensitivity to this phenomenon is demonstrated.

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Simek, V. , Ruzicka, R. , Crha, A. and Reznicek, M. (2015) Reconfigurable Digital Circuits Based on Chip Expander with Integrated Temperature Regulation. Journal of Computer and Communications, 3, 169-175. doi: 10.4236/jcc.2015.311027.

Conflicts of Interest

The authors declare no conflicts of interest.


[1] Stoica, A., Zebulum, R. and Keymeulen, D. (2001) Polymorphic Electronics. Proceedings of Evolvable Systems: From Biology to Hardware Conference, 2210, 291-302.
[2] Sekanina, L., Růzi?ka, R., Va?í?ek, Z., Prokop, R. and Fujcik, L. (2009) REPOMO32—New Reconfigurable Polymorphic Integrated Circuit for Adaptive Hardware. Proceedings of the 2009 IEEE Symposium Series on Computational Intelli-gence—Workshop on Evolvable and Adaptive Hardware, Nashville, 30 March-2 April 2009, 39-46.
[3] R??i?ka, R. and ?imek, V. (2011) Chip Temperature Selfregula-tion for Digital Circuits Using Polymorphic Electronics Principles. Proceedings of 14th Euromicro Conference on Digital System Design, Oulu, 31 August-2 September 2011, 205-212.
[4] Zebulum, R., Stoica, A. and Keymeulen, D. (2000) A Flexible Model of a CMOS Field Programmable Transistor Array Targeted for Hardware Evolution. 3rd International Conference on Evolvable Systems: From Biology to Hardware, Edinburgh, 17-19 April 2000, 274-283.
[5] Cherepacha, D. and Lewis, D. (1996) DP-FPGA: An FPGA Archi-tecture Optimized for Datapaths. Journal on VLSI Design, 4, 329-343.
[6] Nageldinger, U. (2001) Coarse-Grained Reconfigurable Architecture Design Space Exploration. Ph.D. Thesis, Universit?t Kaiserslautern, Kaiserslautern.
[7] Sekanina, L. and R??i?ka, R. (2000) Design of the Special Fast Reconfigurable Chip Using Common FPGA. Proceedings of IEEE Design and Diagnostics of Electronic Circuits and Systems, Smolenice, 5-7 April 2000, 161-168.
[8] R??i?ka, R. (2010) Gracefully Degrading Circuit Controllers Based on Polytronics. Proceedings of 13th Euromicro Conference on Digital System Design, 1-3 September 2010, 809-812.
[9] Sekanina, L., Stare?ek, L., Kotásek, Z. and Gajda, Z. (2008) Polymorphic Gates in Design and Test of Digital Circuits. International Journal of Unconventional Computing, 4, 125-142.
[10] Sekanina, L., R??i?ka, R., Va?í?ek, Z., ?imek, V. and Haná?ek, P. (2013) Implementing a Unique Chip ID on a Reconfigurable Polymorphic Circuit. Information Technology and Control, 42, 7-14.
[11] ?imek, V., R??i?ka, R. and Sekanina, L. (2010) On Analysis of Fabri-cated Polymorphic Circuits. Proceedings of the 13th International IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, Vienna, 14-16 April 2010, 281-284.
[12] Stoica, A., Zebulum, R., Keymeulen, D. and Lohn, J. (2002) On Polymorphic Circuits and Their Design Using Evolutionary Algorithms. Proceedings of IASTED International Confe-rence on Applied Informatics, Insbruck, 18-21 February 2002.
[13] R??i?ka, R., Sekanina, L. and Prokop, R. (2008) Physical Demonstration of Polymorphic Self-Checking Circuits. Proceedings of the 14th IEEE On-Line Testing Sympo-sium (IOLTS), Platja d'Aro, 7-9 July 2008, 31-36.
[14] Miller, J. and Thomson, P. (2000) Cartesian Genetic Pro-gramming. Proceedings of the 3rd European Conference on Genetic Programming EuroGP 2000, 1802, 121-132.
[15] Gajda, Z. and Sekanina, L. (2011) On Evolutionary Synthesis of Compact Polymorphic Combinational Circuits. Journal of Multiple-Valued Logic and Soft Computing, 17, 607-631.
[16] Harman, G. (2010) Wire Bonding in Microelectronics. 3rd Edition, McGraw-Hill, New York.
[17] Miller, L.F. (1972) Thick Film Technology and Chip Joining. Gordon and Breach, New York.
[18] Harper, C.A. (1974) Handbook of Thick Film Hybrid Microelectronics. McGraw-Hill, New York.
[19] Sekanina, L., R??i?ka, R. and Gajda, Z. (2009) Polymorphic FIR Filters with Backup Mode Enabling Power Savings. Proceedings of NASA/ESA Conference on Adaptive Hardware and Systems, San Francisco, 29 July-1 August 2009, 43-50.

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