Design of Secure Microsystems Using Current-to-Data Dependency Analysis


This paper presents a method for designing a class of countermeasures for DPA attacks based on attenuation of current variations. In this class of countermeasures, designers aim at decreasing the dynamic current variations to reduce the information that can be extracted from the current consumption of secure microsystems. The proposed method is based on a novel formula that calculates the number of current traces required for a successful DPA attack using the characteristics of the microsystem current signal and the external noise of the measurement setup. The different stages of the proposed method are illustrated through designing an example current flattening circuit. Meanwhile validity and applicability of the proposed formula is verified by comparing theoretical results with those obtained experimentally for the example circuit. The proposed formula not only estimates the required level of attenuation for a target level of robustness defined by design requirements, it also predicts the effectiveness of a countermeasure using simulation results therefore dramatically reducing the time to design of secure microsystems.

Share and Cite:

H. Vahedi, R. Muresan and S. Gregori, "Design of Secure Microsystems Using Current-to-Data Dependency Analysis," Circuits and Systems, Vol. 4 No. 2, 2013, pp. 137-146. doi: 10.4236/cs.2013.42019.

Conflicts of Interest

The authors declare no conflicts of interest.


[1] P. Kocher, J. Jaffe and B. Jun, “Differential Power Analysis,” LNCS Proceedings of International Cryptology Con ference, Vol. 1666, 1999, pp. 388-397.
[2] K. Tiri and I. Verbauwhede, “Dynamic and Differential CMOS Logic with Signal-Independent Power Consumption to Withstand Differential Power Analysis,” US Patent No. 7692449, 2010.
[3] S. Rammohan, V. Sundaresan and R. Vemuri, “Reduced Complementary Dynamic and Differential Logic: A CMOS Logic Style for DPA-Resistant Secure IC De sign,” Proceedings of International Conference on VLSI Design, Hyderabad, 4-8 January 2008, pp. 699-705.
[4] S. Guilley, L. Sauvage, F. Flament, V. Vong, P. Hoogvorst and R. Pacalet, “Evaluation of Power Constant Dual-Rail Logics Countermeasures against DPA with De sign Time Security Metrics,” IEEE Transactions on Computers, Vol. 59, No. 9, 2010, pp. 1250-1263. doi:10.1109/TC.2010.104
[5] H. Vahedi, S. Gregori and R. Muresan, “On-Chip Power Efficient Current Flattening Circuit,” Journal of Circuits, Systems, and Computers, Vol. 18, No. 3, 2009, pp. 565-579. doi:10.1142/S0218126609005332
[6] S. K. Kim, “Smart Cards Having Protection Circuits Therein That Inhibit Power Analysis Attacks and Methods of Operating Same,” US Patent Application, 2004/ 0158728, 2004.
[7] G. B. Ratanpal, R. D. Williams and T. N. Blalock, “An On-Chip Signal Suppression Countermeasure to Power Analysis Attacks,” IEEE Transactions on Dependable and Secure Computing, Vol. 1, No. 3, 2004, pp. 179-189. doi:10.1109/TDSC.2004.25
[8] T. S. Messerges, “Power Analysis Attacks and Counter measures for Cryptographic Algorithms,” University of Illinois, Chicago, 2000.
[9] S. Mangard, E. Oswald and T. Popp, “Power Analysis Attacks: Revealing the Secrets of Smart Cards,” Springer Science, 2007.
[10] R. Muresan and S. Gregori, “Protection Circuit against Differential Power Analysis Attacks for Smart Cards,” IEEE Transactions on Computers, Vol. 57, No. 11, 2008, pp. 1540-1549. doi:10.1109/TC.2008.107
[11] ATMEL Corporation, ATmega16 Data Sheet.
[12] H. Vahedi, S. Gregori and R. Muresan, “The Effectiveness of a Current Flattening Circuit as Countermeasure against DPA Attacks,” Microelectronics Journal, Vol. 42, No. 1, 2011, pp. 180-187. doi:10.1016/j.mejo.2010.08.011

Copyright © 2021 by authors and Scientific Research Publishing Inc.

Creative Commons License

This work and the related PDF file are licensed under a Creative Commons Attribution 4.0 International License.