1. Introduction
Python SystemVerilog [1] is an emerging methodology for developing advanced verification environments. Python is a high-level programming language with a wide range of libraries and frameworks [2] that can be utilized for various applications. SystemVerilog, on the other hand, is the hardware description language used to describe digital logic circuits and systems. Python SV offers an innovative approach to digital design verification, taking advantage of both Python and SystemVerilog.
2. Python SV Overview
Python SV facilitates the development of verification environments by allowing users to write structures and functions that can be used directly in SystemVerilog. Python-implemented UVM classes are used to construct verification environments, and the SystemVerilog simulator Simulation [3] is used to execute the verification process.
3. Applications of Python SV
Python SV has been used in various digital design verification environments, such as memory [4] controllers, interfaces, and high-speed serial interfaces. In these applications, Python SV has improved the quality of verification tests, enabling the identification of issues that might have been missed in other verification approaches.
4. Benefits of Python SV
Python SV offers several advantages over other verification methodologies.
1) Reduced Development Time: Python SystemVerilog [5] enables users to write simpler tests by reducing the amount of code required. This reduction in code development significantly reduces the development time.
2) Increased Test Coverage: Python SV has been shown to provide high levels of test coverage, ensuring that all scenarios are covered during the verification process.
3) Improved Debugging Capabilities: Python SV provides a more efficient debugging process than other methodologies, allowing users to find issues quickly and accurately.
4) Supports High-Level Abstractions: Python SV offers support for higher-level abstractions when compared to traditional HDLs. This makes designing, simulating, and testing digital designs more manageable, enabling faster execution.
Python SystemVerilog has various applications in the digital design verification process. Here are some of the best scenario uses of Python SV:
1) Memory Interface Verification: Memory interfaces are digital systems’ most complex and critical components. Python SystemVerilog is an ideal verification methodology for memory interfaces, as it is easy to write and execute test cases for different memory operations. Python SV in this application ensures fewer code lines, and high-level abstraction, and provides efficient debugging.
2) High-Speed Serial Interface Verification: Verification of high-speed serial interfaces requires complex verification environments with thousands of test cases. Python SV is an excellent choice for this application because it facilitates the creation of high-speed models, which can simulate and verify the performance of these interfaces with high accuracy.
3) SoC Verification: Python SV verifies SoCs by verifying each module in a system. Python SV simplifies the verification process, by easing the creation of test benches and debug utilities. Python SV used on SoC verification makes it independent of any simulation tool-specific command interface and structured hierarchical connection support.
4) Network-On-Chip (NoC) Verification: Verification of NoCs has become a significant challenge in the design of complex SoCs. Python SV offers several advantages in this scenario, as it facilitates the development of scalable and complex test benches that stimulate different traffic patterns across the NoC topology.
5) Analog-Digital Interface Verification: Python SV is useful for Analog-Digital Interface (ADI) verification as it supports the UVM methodology and facilitates checking the behavior of ADC, DAC, and other analog-digital blocks. This application also highlights the ease of testbench implementation, integrating various Analog Mixed Signal elements in the verification testbench.
Python SV enhances the digital design verification process by providing a powerful and flexible simulation-based verification methodology. Its use cases include each module in a complex SoC design, network-on-chip (NoC) verification, high-speed serial interface verification, and analog-digital interface verification. These best scenario uses to demonstrate the potential of Python SV and highlight its superiority over traditional verification methodologies, such as pure SystemVerilog HDL, VHDL, and C++.
The Python-SV keywords are classified into several categories, including modules, tasks/functions, operators, and control structures. Each category is discussed in detail, providing a thorough understanding of the keywords’ functionalities.
The module category includes keywords such as “module”, “input”, “output”, and “wire”, which are used in defining SystemVerilog modules. The task/function category includes keywords such as “task”, “function”, “if”, “else”, and “case”, which are used in defining testbench components, such as stimulus generators and checkers.
The operator category includes keywords such as “module”, “and”, “or”, “not”, and “xor”, which are used in defining Boolean expressions and digital logic gates. The control structure category includes keywords such as “for”, “while”, “repeat”, and “forever”, which are used in controlling the execution flow of a testbench.
5. How to Connect SystemVerilog with Python
Verification of a digital design often requires an interaction between several language domains (SystemVerilog and C, SystemVerilog and Python, SystemVerilog and e-language, etc.). This article shows you how to set up a connection between SystemVerilog and Python.
SystemVerilog is not able to communicate directly with Python. Instead, the SV code first needs to talk to a C code via a DPI-C, with the C code then able to talk to the Python code. A SystemVerilog-Python connection, therefore, needs to follow certain guidelines, otherwise, the communication will fail. A connection of this kind is shown in the diagram below. (Figure 1)
This interconnection is made up of 4 layers:
1) The User layer
2) The Client layer
3) The Connection layer
4) The Server layer
5.1. The User Layer
The User layer is where the main verification activity takes place. It is the User layer that initiates a connection with another code written in a different programming language. The first step when initiating a connection is to invoke the call_client() function from the Client layer using the address and port number of the server. Optionally, we can provide a message for the Server.
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Figure 1. SystemVerilog communication workflow with Python.
5.2. The Connection Layer
The connection between SystemVerilog and Python works like a Client-Server application connecting 2 entities. The handshake and communication flow between the Client and the Server are shown in Figure 2 below.
In this Client-Server architecture, we are going to use a concept known as a socket, which is an endpoint in a network. A socket is bound to a port of the machine where the application is running. In a Client-Server architecture, both parties must have an associated socket. Moreover, both parties must use a common protocol (TCP or UDP) to be able to understand each other, e.g. when sending and receiving data.
Please note that, as depicted in the diagram, the communication must be initiated by the Client. The Server cannot initiate communication on its own.
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Figure 2. Client-Server communication/handshake flow.
5.3. The Client Layer
The Client layer acts as a proxy between the User layer and the Server layer. A connection with the Server is initiated from within this layer. The Client and the User layers are connected via the DPI-C. For more information on the DPI-C, please refer to this article.
Information (port number, hostname, message to send) received from the User layer is packed into a container struct (client_config) inside the call_client() function. The call_client() function is responsible for:
creating the client socket
managing the connection handshake
handling connection errors
returning the server response to the User layer
5.4. The Server Layer
The Server layer is responsible for providing a response to a user request.
After establishing a connection with the Client, the Server decodes the message received from the Client and generates the message to be sent back to the User. The Server layer and the Client layer are connected via the Connection layer.
In the current implementation, the Client is responsible for closing the connection. The Server catches this event and closes the associated connection handle. There may be different requirements for other applications (the Server is responsible for closing the connection, etc.).
6. Limitations of Python SV
While Python-SystemVerilog (Python-SV) is a promising framework for the design, simulation and verification of digital systems, there are some limitations that need to be considered. The following are some of the major limitations of Python-SV:
1) Learning curve: Python-SV requires programmers to learn two languages—Python and SystemVerilog. The syntax and semantics of these languages are very different and learning both to a high level of proficiency can be time-consuming and challenging.
2) Performance: Python-SV is an interpreted language and is generally slower than compiled SystemVerilog code. This can be a disadvantage when working with very large designs or handling large amounts of data, where performance is critical.
3) Compatibility: Not all SystemVerilog features are supported in Python-SV, which can limit the flexibility of the framework. Python-SV also requires specialized tools that may not be compatible with all SystemVerilog simulators or design tools.
4) Debugging and testing: Debugging Python-SV code can be more challenging than debugging SystemVerilog code due to the two languages’ different natures. Additionally, testing Python-SV code requires specialized tools that are not always readily available.
5) Availability of libraries: While Python has a vast library of useful modules and packages, the same cannot be said for Python-SV. The community around Python-SV is not as extensive as that of Python, and there may be a limited number of libraries available for certain applications.
6) Limited FPGA Support: Some FPGAs do not yet support Python SV verification, limiting the scalability of the methodology. This limits the scope of Python SV with designs that can only be implemented on specific FPGA devices.
7) Backend Compatibility: Python SV’s simulator compatibility is limited. Hence, it cannot work with all available backend system simulators like NC-Verilog.
7. Future Prospects
The use of Python SV is on the rise and could revolutionize the digital design verification process. Several broader adoption frameworks, like Cocotb, enhance Python SV’s capabilities, providing a simulation interchange format between Python and SystemVerilog. Further improvements on Python SV aim to expand its support for a wider range of FPGA devices, improving its applicability.
8. Conclusions
Python SV offers a unique approach to digital design verification, offering faster development, higher test coverage, and more efficient debugging. Its limitations must be taken into account. Nevertheless, its popularity is on the rise, and broader adoption frameworks like Cocotb enhance its application domain. The future potential of Python SV is vast, and further advancements on the development roadmap would increase its overall effectiveness.
Overall, Python-SV is a promising framework for the design and verification of digital systems, offering several benefits over traditional design methodologies. Python-SV is a strengthening technology in the field of digital system design and verification. Its potential has been proven through various papers, and it offers several benefits over traditional design methodologies.
While challenges exist, the ongoing research in this area is expected to overcome these challenges, enabling Python-SV to become a mainstream methodology for digital system design and verification.