Design and Control of an Alternative Buck PWM DC-to-DC Converter

Abstract

The second order dc-to-dc buck converter with input LC filter is widely used in industry. An alternative 4th order converter which has advantages in terms of control design leading to better transient performance is presented. A complete DC (steady state average and ripple quantities) and AC small-signal analyses of this converter for both uncoupled and coupled inductor cases is provided. Conditions for achieving, in a lossless manner, a minimum phase control-to-output transfer function are found, which ameliorates regulator design while maximizing loop bandwidth. A closed loop regulator design procedure is presented and the performance of a design example is examined with a prototype. It is believed that this converter is a good alternative in applications where the second order buck converter augmented with an input filter has been traditionally utilized.

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Simmons, J. and Tymerski, R. (2021) Design and Control of an Alternative Buck PWM DC-to-DC Converter. Journal of Power and Energy Engineering, 9, 43-61. doi: 10.4236/jpee.2021.96004.

1. Introduction

The second order (one inductor, one capacitor) PWM buck dc-to-dc switching converter is a widely used power processing circuit topology. This is partly due to its simple topology and good frequency domain control characteristics, in particular the lack of a non-minimum phase (right half plane) zero common to other topologies. This desirable feature permits a wide regulator loop bandwidth resulting in fast transient response to be achieved to both input voltage and load changes. The buck converter features a DC voltage conversion of V o u t / V g = D where V g , V o u t and D, refer to the input voltage, output voltage and duty ratio, respectively. In this paper, converters that feature this conversion ratio are referred to generically as buck converters.

As the basic buck converter draws a pulsating current from the input, an input LC filter is often used to achieve compliance with regulations regarding electromagnetic interference (EMI). This increases the order of the system to four. This configuration is shown in Figure 1. In [1] [2] and [3], a large number of DC-to-DC converter topologies were derived which feature various conversion ratios. Of the fourth order, two switch (one active switch (transistor) and one passive switch (diode)) converters derived a total of seven feature the conversion ratio of a buck converter. The converter of Figure 1, i.e. the basic buck converter with input filter, is designated as converter D6. The naming convention used in [1] [2] and [3] was one where a converter’s name is designated by its position in a matrix of generated converter topologies where a converter family grouping is designated by an alphabetical character and the following number indicates which of the possible six family members is being referred to.

In this paper, a design approach is presented for an alternative converter configuration, i.e. one of the other six, which has a number of advantages over the D6 converter. This converter is shown in Figure 2 and is designated as converter C1 in [1] [2] and [3]. This converter was also presented in [4], but an analysis or design approach was not given. More recent work featuring the C1 converter has appeared in [5], which was used for a maximum power tracking photovoltaic application. In this paper, an extensive set of constraint equations is derived for use in converter design. Discussions of discontinuous conduction modes of operation, both inductor current and capacitor voltage, are presented here for the first time. Coupling of inductors to minimize output voltage ripple is also discussed. Note that C1 and D6 have exactly the same number and type of components but only the configuration is different. This configuration, under certain component constraints, results in the absence of a right half plane zero in the control to output transfer function thus allowing to achieve an improved dynamic performance with a simplified design approach. This situation will be contrasted with that of the D6 converter in Section 2.

In Section 3, an extensive quantitative analysis of the converter is given. This includes DC, ripple and dynamic small signal analyses and discussion on the

Figure 1. The second order buck converter augmented with an input LC filter. This converter is designated as converter D6 in [1] [2] and [3]. Q and P are the active (transistor) and passive (diode) switches, respectively.

Figure 2. Converter C1 from [1] [2] and [3]. This converter is presented as a viable alternative to converter D6, i.e. the second order buck with input LC filter. Q and P are the active (transistor) and passive (diode) switches, respectively.

avoidance of certain undesirable operating modes, i.e. discontinuous conduction mode and discontinuous voltage mode. This results in the attainment of a set of constraint design equation. Section 4 considers the case of coupling the inductors in an effort to reduce output voltage ripple. A design example is given in Section 5 and performance of the constructed prototype is presented. Finally, in Section 6, the Conclusion, an overview of the paper is summarized.

2. Converters C1 and D6 Control Characteristics Compared

The second order (lossless) buck converter is known to not feature any (finite) zeros. However, when an LC filter precedes the power stage a set of complex right half plane zeros appear in the control (duty ratio) to output transfer function. Using the small-signal state space averaging model [6] the duty ratio to output voltage transfer function numerator polynomial is found to be:

n ( s ) = L 1 C 1 s 2 D 2 L 1 R s + 1 (1)

The presence of the right half plane zero severely restricts the bandwidth of the closed loop system thus limiting dynamic performance. In the presence of parasitic resistive losses in L 1 represented by ESR resistance r L 1 and under the

condition D 2 r L 1 R 1 the numerator may be approximated by

n ( s ) = L 1 C 1 s 2 + ( r L 1 C 1 D 2 L 1 R ) s + 1 (2)

From this it can be seen that zeros can move to the left half plane if r L 1 C 1 D 2 L 1 R > 0 . Alternatively, input filter design for the buck converter has

been approached in the past, see [7] and [8], by finding conditions such that it does not affect the control characteristics of second order buck converter where, as mentioned, no finite zeros are present. This is achieved by incorporation of lossless damping in the input filter, [7] and [8], which increases the number of components needed in the power stage.

In contrast, in a following section it is found that the lossless C1 converter with proper component scaling can feature left half plane zeros and furthermore with the design approach advocated here these zeros can be made to cancel second order poles resulting in an overall second order control to output transfer function.

3. Converter C1 Power Stage Design

3.1. Large-Signal Analysis

In the following a large signal analysis will be performed. This will allow us to determine the average (DC) values of the capacitor voltages and inductor currents. Also, ripple analysis will be performed which will allow us to determine the peak to peak values of the capacitor voltage and inductor current ripples. These analyses use state space models. Operation of the converter will be restricted to the CCM (continuous conduction mode) and CVM (continuous voltage mode). These modes of operation as pertaining to the C1 converter will be discussed subsequently.

Operation in CCM and CVM modes implies that there are two circuit configurations to analyze for the C1 converter. One is where the active switch (e.g. a MOSFET) is ON and the passive switch (e.g. a diode) is OFF, and the other when the reverse switch state occurs. These configurations will be associated with subinterval D T s and D T s , respectively, where D is the duty ratio, D 1 D and T s is the switching period. Initially all parasitics will be ignored and the switches will be considered ideal for simplicity. The state-space model for large signal analysis is given as follows:

x ˙ = A x + B u y = C x + E u (3)

where

A = D A 1 + D A 2

B = D B 1 + D B 2

C = D C 1 + D C 2

E = D E 1 + D E 2

and the state vector, x = [ i 1 , i 2 , v 1 , v 2 ] T , input, u = v g and y = v o u t ( = v 2 in the absence of the equivalent series resistance of C 2 ). The state-space matrices associated with the D T s subinterval, where switch Q in ON and switch P is OFF, are:

A 1 = [ 0 0 0 1 L 1 0 0 1 L 2 1 L 2 0 1 C 1 0 0 1 C 2 1 C 2 0 1 R C 2 ] , B 1 = [ 1 L 1 0 0 0 ]

The state-space matrices associated with the D T s subinterval, where switch Q in OFF and switch P is ON, are:

A 2 = [ 0 0 1 L 1 1 L 1 0 0 0 1 L 2 1 C 1 0 0 0 1 C 2 1 C 2 0 1 R C 2 ] , B 2 = [ 1 L 1 0 0 0 ]

Using (3) the averaged state space matrices A and B are given by:

A = [ 0 0 D L 1 1 L 1 0 0 D L 2 1 L 2 D C 1 D C 1 0 0 1 C 2 1 C 2 0 1 R C 2 ] , B = [ 1 L 1 0 0 0 ]

With capacitor voltage v 2 as output results in:

C 1 = C 2 = C = [ 0 0 0 1 ] , E 1 = E 2 = E = [ 0 0 0 0 ] T

Given a constant input U = V g , the DC input voltage, the steady state vector, X, can be determined as follows [7]:

X = A 1 B U = [ I 1 I 2 V 1 V 2 ] = [ V g D 2 R V g D D R V g V g D ] (4)

The first-order peak-to-peak ripple of the state, Δ x , can be evaluated as shown in [9] as:

Δ x = ( A 1 X + B 1 V g ) D T s = [ Δ i 1 Δ i 2 Δ v 1 Δ v 2 ] = [ V g D D T s L 1 V g D D T s L 2 V g D 2 D T s R C 1 0 ] (5)

Since Δ v 2 is zero, it is necessary to calculate the second-order peak-to-peak ripple of the state, Δ 2 x . This is given by [9]:

Δ 2 x = [ Δ 2 i 1 Δ 2 i 2 Δ 2 v 1 Δ 2 v 2 ] = A Δ x T s 8 = [ V g ( D D ) 2 T s 2 8 R L 1 C 1 V g D 3 D T s 2 8 R L 2 C 1 V g D D T s 2 8 C 1 [ D L 1 + D L 2 ] V g D D T s 2 8 C 2 [ 1 L 1 + 1 L 2 ] ] (6)

With the exception of v 2 , the first-order ripple components are much greater than the second-order components. Therefore, the second-order ripples will be neglected for the inductor currents i 1 and i 2 and capacitor voltage v 1 , but not for the output capacitor voltage v 2 .

3.2. Small-Signal Analysis

The dynamic performance of the converter will be examined by developing a small signal model. In particular the duty ratio control to output transfer function will be derived. This transfer function is important as it forms part of the loop gain of a closed loop system. Particular attention to the presence of any right half plane (RHP) zeros is paid as these zeros will restrict control loop bandwidth thus compromising transient performance. Fortunately constraints can be formulated such that a RHP zero is avoided. Furthermore, other constraints will be given such as a factorization of the denominator polynomial which simplifies the control design process. Initially for simplicity, all elements will be considered as ideal. The state-space equations for the small-signal model are:

x ^ ˙ = A x ^ + B u ^ + [ ( A 1 A 2 ) X + ( B 1 B 2 ) U ] d ^ y ^ = C x ^ + E u ^ + [ ( C 1 C 2 ) X + ( E 1 E 2 ) U ] d ^ (7)

where x ^ = [ i ^ 1 , i ^ 2 , v ^ 1 , v ^ 2 ] T , u ^ = v ^ g and y ^ = v ^ o u t ,

From (7), the control-to-output transfer function, G v d ( s ) v ^ o u t / d ^ ( s ) , can subsequently be determined, with u ^ = 0 :

v ^ o u t d ^ ( s ) = C ( s I A ) 1 [ ( A 1 A 2 ) X + ( B 1 B 2 ) U ] + [ ( C 1 C 2 ) X + ( E 1 E 2 ) U ]

This is evaluated to be:

v ^ o u t d ^ ( s ) = V g s 2 ( L 1 + L 2 ) C 1 + s D ( D L 2 D L 1 ) R + 1 s 4 L 1 L 2 C 1 C 2 + s 3 L 1 L 2 C 1 R + s 2 [ ( L 1 + L 2 ) C 1 + ( D 2 L 1 + D 2 L 2 ) C 2 ] + s D 2 L 1 + D 2 L 2 R + 1 (8)

3.3. Design Constraints

A number of design constraints will now be determined. These arise by considering the following: 1) the conditions to keep the converter in CCM and CVM mode (these are synonymous with the avoidance of discontinuous conduction mode (DCM) or discontinuous voltage mode (DVM) respectively), 2) the maximum inductor current ripples, 3) the maximum output voltage ripple, 4) the avoidance of a RHP zero, and 5) the conditions that make a factorization of the control-to-output transfer function denominator a good approximation. (This factorization is provided as it is convenient in the loop gain design process). To obtain these constraints the results from the large-signal and small-signal analyses will be utilized.

3.3.1. Avoidance of DCM

When switch P is implemented as a diode, the DCM mode may occur. DCM operation arises when the diode current during D T s drops to zero. Such a condition would shut off the diode, resulting in a third topology and therefore a third subinterval which would invalidate the small- and large-signal analyses carried out previously. When the diode is ON it carries the sum of the two inductor currents which is given by i 1 i 2 . Note that current i 2 is summed negatively as a consequence of the current direction shown in Figure 2. To avoid entering DCM, the average-to-peak ripple of the summed currents must be lesser in magnitude than their summed DC values.

I 1 I 2 | Δ i 1 Δ i 2 2 |

Using results obtained from (4) and (5) leads to the constraint:

L 1 | | L 2 R D T s 2 (9)

3.3.2. Avoidance of DVM

DVM arises when the voltage across C 1 drops below zero during D T s turning the diode ON. Having zero voltage across C 1 results in a third topology, characteristic of the DVM mode. DVM is avoided when the average-to-peak

voltage ripple of capacitor C 1 , i.e. Δ v 1 2 , is less than the average capacitor voltage, V 1 . That is

V 1 | Δ v 1 2 |

Substituting results from (4) and (5) and rearranging gives the constraint:

C 1 D 2 D T s 2 R (10)

3.3.3. Acceptable Inductor Current Ripple

Limiting the peak to peak inductor current ripples to 20% of their steady state values results in:

| Δ i 1 | 20 % | I 1 |

and:

| Δ i 2 | 20 % | I 2 |

Substituting from (4) and (5) and rearranging leads to the following constraints on the inductors:

L 1 R D T s 0.2 D (11)

L 2 R T s 0.2 (12)

3.3.4. Acceptable Output Voltage Ripple

For voltage regulators it is desirable to have minimal output voltage ripple. In the absence of ESRs the output voltage v o u t is equal to the v 2 , the voltage across C 2 . Limiting the output voltage ripple to 5% of the DC value gives:

| Δ 2 v 2 | 5 % | V 2 |

Substituting from (4) and (6) and rearranging gives the constraint:

( L 1 | | L 2 ) C 2 > D T s 2 4 (13)

3.3.5. Avoidance of the Right Half Plane Zero

From the numerator of the control-to-output transfer function it can be seen that a RHP zero will exist if the coefficient of s is negative. Thus avoiding the RHP zero requires that:

D L 2 > D L 1 (14)

3.3.6. Symbolic Denominator Factorization

The Bode plot of the control-to-output transfer function will be utilized in a later section to design the feedback loop frequency loop compensation of the C1 converter. Factoring the fourth order polynomial in the denominator of the transfer function into two second order polynomials will make the design of the feedback loop frequency loop compensation conceptually easier as pole-zero cancellation is readily seen. The factorization (given later in Section 5) can be shown to be accurate when the following component constraints apply:

C 1 D 2 C 2 (15)

C 2 D 2 L 2 R 2 (16)

L 1 D 2 L 2 (17)

Note however, there is not a strict requirement to size components to achieve accurate factorization.

4. Inductor Coupling

Coupling the inductors L 1 and L 2 has the potential of reducing the output voltage ripple Δ 2 v 2 . Analysis is provided in the Appendix which shows that the optimum value of M, M o p t , is given by:

M o p t = L 1 (18)

Using the optimum M o p t reduces Δ 2 v 2 by a factor of:

Δ 2 v 2 Δ 2 v 2 M = L 1 + L 2 L 2 (19)

from the uncoupled case. Therefore, coupling the inductors has the potential to reduce the output voltage ripple by as much as 50% for L 1 L 2 or by a negligible percentage if the ratio of inductor values, (defined by parameter α in the Appendix), is large.

5. Design Example

A voltage regulator design example utilizing the C1 converter is presented in this section. The block diagram of this system is shown in Figure 3. The values of the parameters used in this design are listed in Table 1. In the constructed prototype a TL5001 PWM controller IC is used. This device internally provides a triangular waveform with peak-to-peak amplitude of approximately 600 mV which is used as input to the internal PWM comparator. Also provided in this IC is a 1 V reference voltage.

Figure 3. Block diagram of the voltage regulator system with a feedback loop T ( s ) consisting of the C1 converter power stage characterized by its control to output transfer function G v d = v ^ o u t / d ^ , resistive divider gain k, compensator transfer function G c ( s ) , and PWM gain F M = 1 / V M .

Table 1. Parameter values used in the prototype design.

5.1. Power Stage Component Values

Taking into account the previously derived constraints and considering reasonable component ranges, the values shown in (20) were chosen:

L 1 = 330 μ H L 2 = 680 μ H C 1 = 10 μ F C 2 = 10 μ F (20)

Note that for the values chosen, constraints (16) and (17) are not satisfied indicating that the factorization is approximate. However, as previously mentioned, an accurate factorization is not strictly required to achieve an effective design, as will be demonstrated below.

5.2. Frequency Compensation

Frequency compensation is employed to enhance transient performance and provide adequate stability margins. A compensator will be designed by employing asymptotic gain plots. To account for the effects of equivalent series resistance (ESR) of the power stage components on the frequency response, these will need to be introduced into our model given by (8). However, first a factored form of the denominator will be introduced. Equation (21) is a more convenient and factorized form of (8):

G v d ( s ) = V g [ s 2 ( L 1 + L 2 ) C 1 + s D ( D L 2 D L 1 ) R + 1 ] [ ( L 1 + L 2 ) C 1 s 2 + D 2 L 2 R s + 1 ] [ ( L 1 | | L 2 ) C 2 s 2 + L 1 R s + 1 ] (21)

Note that with this factorization, the pole and zero cancellation, which effectively reduces the transfer function to second order, can easily be seen.

To add in the ESRs, the transformations (5.2) are applied to (21).

s L i s L i + r L i , i = 1 , 2 (22)

s C i s C i 1 + s r c i C i , i = 1 , 2 (23)

The resulting terms may be simplified by using the following approximations:

r L i R , i = 1 , 2 (24)

r C i R , i = 1 , 2 (25)

This results in the transfer function:

G v d ( s ) V g ( 1 + s r C 2 C 2 ) [ s 2 L 2 C 1 + s ( ( r L 1 + r L 2 ) C 1 + D ( D L 2 D L 1 ) R + r C 1 C 1 ) + 1 ] [ s 2 L 2 C 1 + s ( D 2 L 2 R + ( r L 1 + r C 1 ) C 1 + r L 2 C 2 ) + 1 ] [ s 2 L 1 C 2 + s ( L 1 R + ( r L 1 + r C 2 ) C 2 ) + 1 ] (26)

From (26) it can be seen that the only break frequency introduced by adding parasitics is a zero due to the ESR of C 2 , which occurs at the frequency ω E S R where:

ω E S R = 1 r C 2 C 2 (27)

The uncancelled second order complex double pole is denoted as ω P where:

ω P = 1 L 1 C 2 (28)

Loop frequency compensation is provided using an “integrator plus lead-lag” compensator. The schematic for which is shown in Figure 4.

The transfer function G c ( s ) of this compensator is given by:

G c ( s ) = ω 0 s ( 1 + s ω z 1 ) ( 1 + s ω z 2 ) ( 1 + s ω p 1 ) ( 1 + s ω p 2 ) (29)

where

ω 0 = 1 R 1 c ( C 2 c + C 3 c ) ω z 1 = 1 R 2 c C 2 c ω z 2 = 1 C 1 c ( R 1 c + R 3 c ) ω p 1 = 1 R 3 c C 1 c ω p 2 = 1 R 2 c C 2 c C 3 c C 2 c + C 3 c (30)

Generally one can separately place the two compensator zeros: one somewhat before ω P and the other at ω P , as is shown in Figure 5. These zeros serve to correct the phase shift from the integrator and ω P , trading a reduced response time for an increase in the loop phase margin. However, for this design both zeros are placed at ω P as a good phase margin is still achieved. The two compensator poles are then placed, one at ω E S R to cancel it out and the other before the switching frequency to improve high frequency roll off. The chosen compensator pole and zero frequencies, in Hertz, are:

f z 1 = 2.77 kHz f z 2 = 2.77 kHz f p 1 = 60 kHz f p 2 = 90 kHz (31)

From Figure 3, it can be seen that the loop gain is given by:

T ( s ) = k G c ( s ) F M G v d ( s ) (32)

Figure 4. Integrator plus lead-lag compensator.

Figure 5. Bode magnitude asymptotes for the control-to-output transfer function G v d ( s ) , the integrator with lead-lag compensator gain G c ( s ) , and the loop gain T ( s ) . The horizontal axis frequency in Hz. on a log scale and the vertical axis is magnitude of the appropriate transfer function on a dB scale. The magnitude annotations represent absolute gain values varying with frequency f along the various straight line segments.

where the modulator gain F M 1 V M . The asymptotic gains of G v d ( s ) , G c ( s ) ,

and T ( s ) are given in Figure 5. These plots have been annotated by the absolute gains that appear along each straight line segment. In particular, in the vicinity of the desirable unity gain crossover frequency f C of the loop gain T ( s ) , that is, in the frequency interval f [ f P , f p 2 ] , the gain is given by:

| T ( j 2 π f ) | f [ f P , f p 2 ] = k F M V g f 0 f z 2 f z 1 f (33)

Setting f = f C in (33) and making f 0 ( = ω 0 2 π ) the subject of the expression gives

f 0 = f z 1 f C k F M V g f z 2 (34)

Choosing a crossover frequency f C of 10 kHz results in:

f 0 = 3 kHz (35)

The chosen component values for the compensator which satisfy the determined gain and zero and pole locations are:

R 1 c = 47 k Ω R 2 c = 56 k Ω R 3 c = 2.2 k Ω C 1 c = 1.2 nF C 2 c = 1 nF C 3 c = 33 pF (36)

Figure 6 shows the Bode plot of the loop gain evaluated by MATLAB using the exact transfer function expression of G v d . The achieved unity gain crossover frequency is seen to be 16 kHz, which is slightly greater than the 10 kHz specified due the approximate formulas used. The phase margin is seen to be 56.4˚. Thus, with a switching frequency of 100 kHz, a wide loop bandwidth can be seen to be achieved with a good level of stability margin.

A constructed prototype of a closed loop voltage regulator featuring a C1 converter is shown in Figure 7. This schematic also shows a voltage switching circuit by which the input voltage to the converter, v g , can be switched between two levels. Furthermore, the schematic also shows an output load switching circuit by which the load resistance is switched between two values.

Figure 6. Loop gain of the voltage regulator system using the C1 converter power stage. The unity gain crossover frequency is confirmed to be 16 kHz and the phase margin is 56.4˚. The converter switching frequency is 100 kHz.

Figure 8 shows the converter output voltage transient response when the converter input voltage v g is stepped from 10 V to 11 V and then back to 10 V. Figure 9 shows the output voltage response to a step load change. The load changes from 5 ohms to 5 ohms in parallel with 10 ohms, i.e. 3.3 ohms. These responses confirm the wide bandwidth and stability margin achieved. (Note: not shown in the schematic is a series connection of a 10 ohm resistor and 47 μF capacitor that was placed across the capacitor which is between the two converter inductors. This dampened the slight oscillation that appeared in the output responses. However, this damping network is not seen as essential.)

Figure 7. Constructed prototype of the C1 converter in closed loop, together with an input voltage switching circuit and also an output load switching circuit.

Figure 8. Output voltage response due to step input voltage change. Input voltage Vg is stepped from 10 V to 11 V and then back to 10 V. Top curve: gate drive signal to the 2N7000 Mosfet of the voltage stepping circuit, vertical scale: 5 V/div. Middle curve: input voltage to the C1 converter, showing the step changes between 10 V and 11 V, vertical scale: 2 V/div. Bottom curve: output voltage changes, vertical scale: 50 mV/div.

Figure 9. Output voltage response due to step load changes. The load changes from 5 ohms to 5 ohms in parallel with 10 ohms. Top curve: gate drive signal to the IRF530 Mosfet of the load stepping circuit, vertical scale: 5 V/div. Bottom curve: output voltage changes, vertical scale: 50 mV/div.

5.3. Inductor Coupling Consideration

Although not adopted in our design it is possible to couple the inductors which can enhance ripple performance. For the present design with the component values of L 1 and L 2 as determined previously, the output voltage ripple can be reduced by:

Δ 2 v 2 Δ 2 v 2 M Δ 2 v 2 = L 1 L 1 + L 2 = 11.5 % (37)

6. Conclusions

Complete DC (steady state average and peak-to-peak ripple values) and small-signal AC analyses of the C1 converter have been presented. Furthermore, a design approach has been elucidated. The process for determining reasonable component values from constraints avoiding DCM and DVM operation, avoiding a RHP zero, and ensuring the validity of a denominator factorization of the control-to-output transfer function has been outlined and carried out along with the design of a feedback loop frequency compensator using asymptotic gain plots, improving transient step response and system stability. The denominator factorization of the control-to-output transfer function and corresponding constraints allow the C1 converter to behave similar to a second-order converter, with a second-order complex double zero canceling a second-order complex double pole. The impact of introducing mutual inductance M between the two inductors in the power stage of the C1 converter was also investigated, yielding an expression for the optimum mutual inductance M o p t , the benefits of an avoided RHP zero, and a simple equation to determine the decrease in output voltage ripple.

In summary, the benefits of the C1 converter, primarily in terms of favorable control characteristics, have been examined. Furthermore, a number of constraints have been derived which can be used in the design process to optimize both steady state and small signal performance. A design example was presented which validated the approach. It is believed that the C1 converter is a viable alternative in applications where the second order buck converter augmented with an input filter has been traditionally utilized.

Acknowledgements

The following former students in the Electrical and Computer Engineering Department at Portland State University are acknowledged for prototype construction and for providing the oscillograms shown in this paper: Dawei Che, Midrar Adham, Gordon Hoffman and Ali Sheikly.

Appendix A

Inductor Coupling

Coupling the inductors L 1 and L 2 has the potential of reducing the output voltage ripple Δ 2 v 2 . The output voltage ripple with a nonzero mutual inductance M will be denoted Δ 2 v 2 M . For some switched power converters output voltage ripple v 2 can be completely nulled with inductor coupling, however for the C1 converter only reduction is possible. An optimum value of M, denoted M o p t , will first be derived for the C1 converter based on the expressions Δ 2 v 2 and Δ 2 v 2 M . The effect of M on G v d ( s ) will then be investigated to determine whether M o p t is practical and to point out any advantages or disadvantages to inductor coupling.

1) Optimum value for M

The mutual inductance M between two inductors L 1 and L 2 can be expressed as:

M = k L 1 L 2 (38)

where the constant k is the coefficient of coupling that is restricted to 1 k 1 . Defining α to be the ratio between L 1 and L 2 such that:

α L 2 L 1 L 2 = α L 1 (39)

Substituting (39) into (38) gives a new expression for M:

M = L 1 k α (40)

Obtaining an expression for Δ 2 v 2 M is accomplished by utilizing the procedure in [4] as was done with the uncoupled case. Introducing M affects the inductor voltages such that:

v L 1 = L 1 d i 1 d t + M d i 2 d t (41)

v L 2 = M d i 1 d t + L 2 d i 2 d t (42)

With (7.1) considered an expression for Δ 2 v 2 M is found:

Δ 2 v 2 M = V g D D T s 2 8 C 2 L 1 + L 2 2 M L 1 L 2 M 2 (43)

Equation (43) reduces to the result in (6) for M = 0 . Comparing (6) to (43) to consider the effect of M means that only the factor containing M is of interest, which will be treated as a function f, where:

f ( M ) = L 1 + L 2 2 M L 1 L 2 M 2 (44)

It can be seen from (44) that the denominator is only affected by the magnitude of M and is independent of the sign while the numerator clearly reduces with a positive M and increases with a negative M, so that a negative M actually increases the output ripple, Δ 2 v 2 M from the uncoupled case. Substituting (39) and (40) into (44) and dropping factors that are not affected by M:

f ( M ) = L 1 + L 2 2 M L 1 L 2 M 2 = 1 + α 2 k α L 1 α ( 1 k 2 ) = f ( α , k ) (45)

Differentiating (45) with respect to α and k:

f α = 1 k α L 1 α 2 ( k 2 1 ) (46)

f k = 2 ( k 2 α k ( α + 1 ) + α ) L 1 ( k 2 1 ) 2 α (47)

reveals that both f α and f k go to zero when:

k α = 1 (48)

This means that f is at its minimum when (48) is satisfied. Substituting (48) into (40) we find the optimum value of M:

M o p t = L 1 (49)

2) Effect of Mutual Inductance

The G v d ( s ) with a nonzero M becomes:

G v d ( s ) = V g ( s 2 N 2 + s N 1 + 1 ) s 4 D 4 + s 3 D 3 + s 2 D 2 + s D 1 + 1 (50)

where

N 1 = D R [ D L 1 + D L 2 + ( 2 D 1 ) M ] N 2 = ( L 1 + L 2 2 M ) C 1 D 1 = D 2 L 1 + D 2 L 2 + 2 D D M R D 2 = ( L 1 + L 2 2 M ) C 1 + ( D 2 L 1 + D 2 L 2 + 2 D D M ) C 2 D 3 = ( L 1 L 2 M 2 ) C 1 R D 4 = ( L 1 L 2 M 2 ) C 1 C 2 (51)

The RHP zero is avoided when coefficient N 1 is positive. Substituting the optimum value of M, i.e. M o p t = L 1 , into N 1 leads to:

N 1 = D D R ( L 2 L 1 ) (52)

so the RHP zero is avoided when L 2 > L 1 , a condition which is already satisfied by the denominator factorization constraint D L 2 L 1 . The complex second order zero and pole locations are contained in the coefficients N 2 and D 4 , respectively. Substituting M o p t into N 2 and applying the aforementioned constraint leads to:

N 2 = ( L 2 L 1 ) C 1 L 2 C 1 (53)

which is the same coefficient used in the uncoupled case, therefore the zero location used in the compensator design is still valid. Now substituting M o p t into D 4 and also applying the denominator factorization constraint gives:

D 4 = L 1 ( L 2 L 1 ) C 1 C 2 L 1 L 2 C 1 C 2 (54)

It is evident that the approximate pole locations determined by the denominator factorization are also still valid. Taking a look at D 3 in a similar fashion shows that it is also unchanged:

D 3 = ( L 1 L 2 M 2 ) C 1 R L 1 L 2 C 1 R (55)

suggesting that there is a negligible change in the Q factors of the complex second order double poles as well.

With the RHP zero avoided and the complex second order zero and pole locations still valid, coupling L 1 and L 2 only has the disadvantages associated with physical implementation. Using the optimum M reduces Δ 2 v 2 by a factor of:

Δ 2 v 2 Δ 2 v 2 M = L 1 + L 2 L 2 (56)

from the uncoupled case, thus coupling the inductors can either reduce the output voltage ripple by as much as 50% for L 1 L 2 or by a negligible percentage for a very large α .

Conflicts of Interest

The authors declare no conflicts of interest regarding the publication of this paper.

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