Author(s)

Chin-Hsin Lin, Marek Syrzycki

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This paperpresents a single-stage Vernier Time-to-Digital Converter (VTDC) that utilizes the dynamic-logic phase detector. The zero dead-zone characteristic of this phase detector allows for the single-stage VTDC to deliver sub-gate delay time resolution. The single-stage VTDC has been designed in 0.13μm CMOS technology. The simulation results demonstrate a linear input-output characteristic for input dynamic range from 0 to 1.6ns with a time resolution of 25ps.

Vernier Time-to-Digital Converter, Dynamic-Logic Phase Frequency Detector

C. Lin and M. Syrzycki, "Single-Stage Vernier Time-to-Digital Converter with Sub-Gate Delay Time Resolution," Circuits and Systems, Vol. 2 No. 4, 2011, pp. 365-371. doi: 10.4236/cs.2011.24050.