Circuits and Systems

Volume 7, Issue 9 (July 2016)

ISSN Print: 2153-1285   ISSN Online: 2153-1293

Google-based Impact Factor: 0.48  Citations  h5-index & Ranking

Error Correction Circuit for Single-Event Hardening of Delay Locked Loops

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DOI: 10.4236/cs.2016.79210    1,998 Downloads   2,747 Views  Citations


In scaled CMOS processes, the single-event effects generate missing output pulses in Delay-Locked Loop (DLL). Due to its effective sequence detection of the missing pulses in the proposed Error Correction Circuit (ECC) and its portability to be applied to any DLL type, the ECC mitigates the impact of single-event effects and completes its operation with less design complexity without any concern about losing the information. The ECC has been implemented in 180 nm CMOS process and measured the accuracy of mitigation on simulations at LETs up to 100 MeV-cm2/mg. The robustness and portability of the mitigation technique are validated through the results obtained by implementing proposed ECC in XilinxArtix 7 FPGA.

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Balaji, S. and Ramasamy, S. (2016) Error Correction Circuit for Single-Event Hardening of Delay Locked Loops. Circuits and Systems, 7, 2437-2442. doi: 10.4236/cs.2016.79210.

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