Author(s)

Jamuna Ramasamy¹, Sathishkumar Nagarajan²

¹Department of Electronics & Communication Engineering, SNS College of Engineering, Coimbatore, India.
²Department of Electronics & Communication Engineering, Sri Ramakrishna Engineering College, Coimbatore, India.

It is critical in terms of approximate computation errors in VLSI multiplier circuits are increasing with technology scaling. The most common method for fast and energy efficient execution of multiplication result is approximation of operands. But this traditional approximate result is not suitable for image processing applications. This paper proposes the two architectures of high accurate hybrid segment approximate multiplier (HSAM) and enhanced HSAM for image compression. Existing static segment method based approximate multiplier is not suitable for certain accurate applications and dynamic segment method based approximate multiplier is not suitable for cost efficient applications. The proposed work combines the advantages of both static segment method and dynamic segment method to drive the efficiency in accuracy and cost. The proposed approximate multipliers HSAM8 × 8 and EHSAM8 × 8 provide 99.85% and 99.999% accuracy respectively for various inputs. The proposed HSAM consumes less energy with small increase of area overhead. The proposed EHSAM consumes less energy without any area overhead. The proposed HSAM and EHSAM is improved the speed by 40% and 85% compared to the existing SSM8 × 8 technique.

Communication, Timing Synchronization, FPGA, Multipliers, Parallel Processing, Power, Delay

Ramasamy, J. and Nagarajan, S. (2016) Hybrid Segment Approximate Multiplication for Image Processing Applications. Circuits and Systems, 7, 1701-1708. doi: 10.4236/cs.2016.78147.