Current Mode Logic Testing of XOR/XNOR Circuit: A Case Study


This paper investigates the issue of testing Current Mode Logic (CML) gates. A three-bit parity checker is used as a case study. It is first shown that, as expected, the stuck-at fault model is not appropriate for testing CML gates. It is then proved that switching the order in which inputs are applied to a gate will affect the minimum test set; this is not the case in conventional voltage mode gates. Both the circuit output and its inverse have to be monitored to reduce the size of the test set.

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M. Fouad, H. Amer, A. Madian and M. Abdelhalim, "Current Mode Logic Testing of XOR/XNOR Circuit: A Case Study," Circuits and Systems, Vol. 4 No. 4, 2013, pp. 364-368. doi: 10.4236/cs.2013.44049.

1. Introduction

Static CMOS logic style is commonly used in the design of digital integrated circuits due to its advantages such as very low static power dissipation, high packing density and wide noise margins. However, this logic family is highly susceptible to environmental noise sources [1]. Also, its maximum operating frequency is orders of magnitudes less than fT of the MOS device. It also suffers from large dynamic power dissipation at high frequencies.

High speed logic circuits usually use current mode logic (CML) design. First, bipolar transistors were used to implement this type of logic [2]. Currently, CML is most commonly used.

Designing a high-speed CMOS circuit operating near fT of the MOS device is very challenging. System blocks in a Giga-bit communication system need to be realized by very simple circuits utilizing minimum number of active devices. High-speed signal processing circuits in a communication transceiver should not use PMOS devices due to their inferior unity-gain frequency. Additional design constraints are needed for very high speed signal processing. On the other hand, buffers are the circuit core of many high-speed blocks within a communication transceiver and a serial link. Front-end tapered buffer chain, serial-to-parallel converters, clock and data recovery (CDR), multiplexers and demultiplexers all use high-speed buffers with a robust performance in the presence of noise. The electromagnetic coupling causes serious operational malfunctioning in the circuits, particularly single-ended circuits [3,4].

The CML circuits can operate with lower signal voltage and higher operating frequency at lower supply voltage than CMOS circuits can. Due to their superior performance, CML buffers are the best choice for highspeed applications. As a consequence, it is essential to have a systematic approach to optimally test CML gates.

In [5], testing for catastrophic open and short faults has been addressed on analog MOS current mode circuits. A CMOS transconductor testing has been introduced using 0.18 µm technology provided by MOSIS. The circuit was modeled in PSPICE and five faults per transistor are assumed. A single fault was injected into the circuit at a time. The total fault coverage was 93%. In [6], the same circuit has been tested using 90nm technology from MOSIS, modeled in PSPICE. This work considered six faults model per transistor. The total fault coverage was 94.4%.

In this paper, an attempt to test CML circuits is introduced. A 3-input parity checker will be studied and the minimum test set will be determined in order to obtain a 100% coverage. Five faults will be assumed per transistor but only one fault will be assumed at a time [5,7-9]. The minimum test set is then compared to the one obtained in case of a similar circuit implemented with conventional voltage mode gates and assuming a single stuck-at fault at a time. It will first be shown that, as expected, the single stuck-at fault model is not appropriate for CML. It will then be shown (and this is the main contribution of this paper) that the order of input application to an Exclusive-Or gate may affect the size of the minimum test set. It is important to remember, however, that the results of this case study cannot be generalized since only one circuit and one type of gate, have been investigated.

The rest of this paper is organized as follows: Section 2 has the description of the circuit under test. Section 3 describes the testing methodology and the fault model used throughout this study. In Section 4, the ELDO simulation results are presented and the minimum test set is found. Finally, the paper is concluded in Section 5.

2. Description of the Circuit under Test

A three input parity checker circuit using two-input XOR gates is shown in Figure 1. For simplicity, the input vector will follow the format CBA and converted to decimal, i.e., input vector 4 will refer to CBA = 100. A CMOS CML two-input XOR/XNOR gate is implemented as shown in Figure 2 [10]. The circuit produces the output and its inverse. The MOS model uses the 90 nm technology from MOSIS. The supply and bias voltages are +1 V. Note that the third input (C) is connected to the lower transistors of the rightmost XOR gate (XOR2) but it could also be connected to the upper transistors. The importance of this issue will be addressed later in this paper. In Figure 1, Myx refers to transistor x (1 - 9) in gate y (1 or 2). For example, M12 is transistor 2 in the leftmost XOR gate.

3. Testing Methodology

Several fault models are reported in the literature for MOS transistors [5,7-8]. In this paper, the five fault model will be used: Drain-Gate short circuit (DG), DrainSource short circuit (DS), Source-Gate short circuit (SG), open circuit at Drain (OD) and open circuit at source (OS). The number of transistors is 9 transistors per gate and the circuit has two gates; hence, the total number of faults considered in this circuit is 90. Only one catastrophic fault is assumed at a time [7]. The two fault-free outputs of the circuit are applied to two CMOS inverters that represent the load. Alternatively, these two inverters can represent the front end of the Automatic Test Equipment (ATE). For every fault, the circuit outputs are compared to the fault-free outputs. The ELDO simulator from MENTOR Graphics is used in the analysis [11]. Both the XOR and XNOR outputs of the second gate are used in the comparison. For any input vector, if at least one output is different from the corresponding fault-free output, the fault is considered to be detectable by this input vector.

Figure 1. Three bit parity checker.

Figure 2. Transistor level circuit diagram.

It is observed that the XOR and XNOR outputs sometimes fall in the undefined region of the inverters representing the test equipment. In other words, the output voltage is higher that Vil and lower than Vih. The inverter has Vil = 0.5 V and Vih = 0.6V. Furthermore, the outputs of the circuit under test may be affected by noise. The noise amplitude level is usually ±5% of the supply voltage, i.e., 0.05 V in this study [12]. Hence, it will be assumed that any input vector producing an output voltage between 0.5 and 0.6 V for a specific fault cannot be used as a test vector for that fault because noise added to this output may toggle its digital value at the outputs of the inverters (front end of the test equipment). These unsafe input vectors will be excluded from the test set and only safe test vectors will be considered.

For example, Table 1 has the results of the ELDO simulations for the circuit with faults in transistor M11. C and its inverse C’ are connected to the lower transistors M21 and M22. The circuit is simulated with one fault at a time. For every fault, BI is the actual value of the voltage at the XOR/XNOR output and AI is the output of the inverter representing the front end of the test equipment. If AI is the incorrect logic value, the input vector is considered to have detected the fault. The rightmost two columns have the fault-free values for comparison. In Table 1, it is observed that there are several unsafe vectors. Any BI with a value between 0.5 V and 0.6 V indicates that the vector producing that value may not detect that specific fault. The SG fault may not be detected by input vector 7 (CBA = 111) because BI/OUT1 is 0.53 V. Noise on this output could increase it and cause the inverter output (AI) to switch from a logic 1 to a logic 0. The fault-free output of the circuit for input vector 7 being a logic 1, the output of the inverter should be a logic 0. Hence, the noise may cause the output of the inverter to be correct and the fault is not detected. Consequently, input vector 7 will be considered as an unsafe test vector that cannot detect the SG fault in M11.

4. Minimum Test Set

Table 2 shows the ELDO simulation results for all faults

Conflicts of Interest

The authors declare no conflicts of interest.


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