[1]
|
Mead, C.A. (1994) Scaling of MOS Technology to Submicroometer Feature Sizes. Analog Integrated Circuits and Signal Processing, 6, 9-25. https://doi.org/10.1007/BF01250732
|
[2]
|
Taur, Y., Member, S., Buchanan, D.A., Chen, W.E.I., Frank, D.J., Ismail, K.E. and Wong, H. (1997) CMOS Scaling into the Nanometer Regime. Proceedings of the IEEE, 85, 486-504. https://doi.org/10.1109/5.573737
|
[3]
|
Breed, A.A. and Roenker, K.P. (2008) Comparison of the Scaling Characteristics of Nanoscale SOI N-Channel Multiple-Gate MOSFETs. Analog Integrated Circuits and Signal Processing, 56, 135-141. https://doi.org/10.1007/s10470-007-9129-6
|
[4]
|
Foty, D. (1999) Perspectives on Analytical Modeling of Small Geometry MOSFETs in SPICE for Low Voltage/Low Power CMOS Circuit Design. Analog Integrated Circuits and Signal Processing, 21, 229-252. https://doi.org/10.1023/A:1008373903657
|
[5]
|
Zou, L. and Larsen, T. (2012) Modeling of Substrate Leakage Currents in a High-Voltage CMOS Rectifier. Analog Integrated Circuits and Signal Processing, 71, 231-236. https://doi.org/10.1007/s10470-011-9633-6
|
[6]
|
Kaizerman, A., Fisher, S. and Fish, A. (2013) Subthreshold Dual Mode Logic. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 21, 979-983. https://doi.org/10.1109/TVLSI.2012.2198678
|
[7]
|
Bol, D., Ambroise, R., Flandre, D. and Legat, J.-D. (2009) Interests and Limitation of Technology Scaling for Subthreshold Logic. IEEE Transactions on Very Large Scale Integration (VLSI) System, 17, 1508-1519. https://doi.org/10.1109/TVLSI.2008.2005413
|
[8]
|
Sun, S.W. and Tsui, P.G.Y. (1995) Limitation of CMOS Supply-Voltage Scaling by MOSFET Threshold-Voltage Variation. IEEE Journal of Solid-State Circuits, 30, 947-949. https://doi.org/10.1109/4.400439
|
[9]
|
De, V. and Borkar, S. (1999) Technology and Design Challenges for Low Power and High Performance. Proceeding of International Symposium on Low Power Electronics and Design, San Diego, CA, 16-17 August 1999, 163-168. https://doi.org/10.1145/313817.313908
|
[10]
|
Rao, R., Srivastava, A., Blaauw, D. and Sylvester, D. (2004) Statistical Analysis of Subthreshold Leakage Current for VLSI Circuits. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 12, 131-139. https://doi.org/10.1109/TVLSI.2003.821549
|
[11]
|
Ki, K. and Kim, K.Y. (2009) Statistical Timing and Leakage Power Analysis of PD-SOI Digital Circuits. Analog Integrated Circuits and Signal Processing, 60, 127-136. https://doi.org/10.1007/s10470-008-9220-7
|
[12]
|
Xue, J., Li, T., Deng, Y. and Yu, Z. (2010) Full-Chip Leakage Analysis for 65 nm CMOS Technology and Beyond. Integration, the VLSI Journal, 43, 353-364. https://doi.org/10.1016/j.vlsi.2010.05.002
|
[13]
|
Keshavarzi, A., Roy, K., Member, S. and Hawkins, C.F. (2000) Intrinsic Leakage in Deep Submicron CMOS ICs—Measurement-Based Test Solutions. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 8, 717-723. https://doi.org/10.1109/92.902266
|
[14]
|
Lorenzo, R. and Chaudhury, S. (2016) Review of Circuit Level Leakage Minimization Techniques in CMOS VLSI Circuits. IETE Technical Review, 33, 1-23. https://doi.org/10.1080/02564602.2016.1162116
|
[15]
|
Henson, W.K., Yang, N., Kubicek, S., Vogel, E.M., Wortman, J.J., Member, S., et al. (2000) Analysis of Leakage Currents and Impact on Off-State Power Consumption for CMOS Technology in the 100-nm Regime. IEEE Transactions on Electron Devices, 47, 1393-1400. https://doi.org/10.1109/16.848282
|
[16]
|
Bikki, P. and Karuppanan, P. (2016) Analysis of Low Power and Small Swing Self-Biasing CMOS Design. Fareast Journal of Electronics and Communication, 3, 245-261. https://doi.org/10.17654/ECSV3PI16245
|
[17]
|
Fjeldly, T.A., Member, S. and Shur, M. (1993) Threshold Voltage Modeling and the Subthreshold Regime of Operation of Short-Channel. IEEE Transactions on Electron Devices, 40, 137-145. https://doi.org/10.1109/16.249436
|
[18]
|
Tsang, T.K., El-gamal, N.M., Iniewski, K., Townsend, K.A., Haslett, J.W. and Wang, Y. (2007) Current Status of CMOS Low Voltage and Low Power Wireless IC Designs. Analog Integrated Circuits and Signal Processing, 53, 9-18. https://doi.org/10.1007/s10470-006-9019-3
|
[19]
|
Serra-Graells, F. and Huertas, J.L. (2003) 1 V CMOS Subthreshold Log Domain PDM. Analog Integrated Circuits and Signal Processing, 34, 183-187. https://doi.org/10.1023/A:1022545414777
|
[20]
|
Singh, S.K. and Kaushik, B.K. (2013) A Novel Approach to Reduce Leakage Current in ULP SRAM. IETE Technical Review, 59, 704-708. https://doi.org/10.4103/0377-2063.126968
|
[21]
|
Prasad, G. and Anand, A. (2015) Statistical Analysis of Low-Power SRAM Cell Structure. Analog Integrated Circuits and Signal Processing, 82, 349-358. https://doi.org/10.1007/s10470-014-0463-1
|
[22]
|
Jovanovic, B., Brum, R.M. and Torres, L. (2014) Evaluation of Hybrid MRAM/ CMOS Cells for “Normally-Off and Instant-On” Computing. Analog Integrated Circuits and Signal Processing, 81, 607-621. https://doi.org/10.1007/s10470-014-0427-5
|
[23]
|
Lo, C.H. and Huang, S.Y. (2011) P-P-N Based 10T SRAM Cell for Low-Leakage and Resilient Subthreshold Operation. IEEE Journal of Solid-State Circuits, 46, 695-704. https://doi.org/10.1109/JSSC.2010.2102571
|
[24]
|
Zhang, L.-J., Wu, C., Ma, Y.-Q., Zheng, J.-B. and Mao, L.-F. (2011) Leakage Power Reduction Techniques of 55 nm SRAM Cells. IETE Technical Review, 28, 135-145. https://doi.org/10.4103/0256-4602.78105
|
[25]
|
Roy, K., Mukhopadhyay, S. and Mahmoodi-Meimand, H. (2003) Leakage Current Mechanisms and Leakage Reduction Techniques in Deep-Submicrometer CMOS Circuits. Proceedings of the IEEE, 91, 305-327. https://doi.org/10.1109/JPROC.2002.808156
|
[26]
|
Calimera, A., MacIi, A., MacIi, E. and Poncino, M. (2012) Design Techniques and Architectures for Low-Leakage SRAMs. IEEE Transactions on Circuits and Systems I: Regular Papers, 59, 1992-2007. https://doi.org/10.1109/TCSI.2012.2185303
|
[27]
|
Tanizawa, M., Ikeda, M., Kotani, N., Tsukamoto, K. and Horie, K. (1993) A Complete Substrate Current Model Including Band-to-Band Tunneling Current for Circuit Simulation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 12, 1749-1757. https://doi.org/10.1109/43.248086
|
[28]
|
Antognetti, P., Caviglia, D.D. and Profumo, E. (1982) CAD Model for Threshold and Subthreshold Conduction in MOSFET’s. IEEE Journal of Solid-State Circuits, 17, 454-458. https://doi.org/10.1109/JSSC.1982.1051759
|
[29]
|
Narendra, S., De, V., Borkar, S., Antoniadis, D. and Chandrakasan, A. (2002) Full-Chip Sub-Threshold Leakage Power Prediction Model for Sub-0.18 um CMOS. International Symposium on Low Power Electronincs and Design, Monterey, CA, 12-14 August 2002, 19-23. https://doi.org/10.1145/566408.566415
|
[30]
|
Pavasovic, A., Andreou, A.G. and Westgate, C.R. (1994) Characterization of Subthreshold MOS Mismatch in Transistors for VLSI Systems. Analog Integrated Circuits and Signal Processing, 6, 75-85. https://doi.org/10.1007/BF01250737
|
[31]
|
Chang, I.J., Park, S.P. and Roy, K. (2010) Exploring Asynchronous Design Techniques for Process-Tolerant and Energy-Efficient Subthreshold Operation. IEEE Journal of Solid-State Circuits, 45, 401-410. https://doi.org/10.1109/JSSC.2009.2036764
|
[32]
|
Guo, J., Liu, Y., Chou, M.H., Wang, M.T. and Shone, F. (1998) A Three-Terminal Band-Trap-Band Tunneling Model for Drain Engineering and Substrate Bias Effect on GIDL in MOSFET. IEEE Transactions on Electron Devices, 45, 1518-1523. https://doi.org/10.1109/16.701483
|
[33]
|
Ghodsi, R., Sharifzadeh, S. and Majjiga, J. (1998) Gate-Induced Drain-Leakage in Buried-Channel PMOS: A Limiting Factor in Development. IEEE Electron Device Letters, 19, 354-356. https://doi.org/10.1109/55.709642
|
[34]
|
Xu, Y., Chi, B. and Wang, Z. (2013) Gate-Leakage Compensation Scheme for Programmable SI-DAC of Modulator in Deep Sub-Micron. Analog Integrated Circuits and Signal Processing, 76, 155-160. https://doi.org/10.1007/s10470-013-0073-3
|
[35]
|
Rosar, M., Leroy, B. and Schweeger, G. (2000) A New Model for the Description of Gate Voltage and Temperature Dependence of Gate Induced Drain Leakage (GIDL) in the Low Electric Field Region. IEEE Transactions on Electron Devices, 47, 154-159. https://doi.org/10.1109/16.817581
|
[36]
|
Yuan, X., Park, J.E., Wang, J., Zhao, E., Ahlgren, D.C., Hook, T., et al. (2008) Gate-Induced-Drain-Leakage Current in 45-nm CMOS Technology. IEEE Transactions on Device and Materials Reliability, 8, 501-508. https://doi.org/10.1109/TDMR.2008.2002350
|
[37]
|
Ana, F. and Najeeb-Ud-Din (2012) Suppression of Gate Induced Drain Leakage Current (GIDL) by Gate Work Function Engineering: Analysis and Model. Journal of Electronic Devices, 13, 984-996.
|
[38]
|
Gupta, A.D.A.S. and Lahiri, S.K. (1990) An Aanalytical Model of Punchthrough Voltage of Short Channel MOSFETS with Nonuniformly Doped Channels. Solid-State Electronics, 33, 395-400. https://doi.org/10.1016/0038-1101(90)90041-C
|
[39]
|
Keshavarzi, A., Roy, K., Lafayette, W. and Hawkins, C.F. (1997) Intrinsic Leakage in Low Power Deep Submicron CMOS ICs. International Test Conference, 6 November 1997, 146-155. https://doi.org/10.1109/test.1997.639607
|
[40]
|
Fu, K.Y. and Tsang, Y.L. (1997) On the Punchthrough Phenomenon in Submicron MOS Transistors. IEEE Transactions on Electron Devices, 44, 847-855. https://doi.org/10.1109/16.568048
|
[41]
|
Fu, K.-Y. and Tsang, Y.L. (1997) Punchthrough Currents in Sub-Micron Short Channel MOS Transistors. Solid-State Electronics, 41, 435-439. https://doi.org/10.1016/S0038-1101(96)00103-7
|
[42]
|
Dennard, R., Gaensslen, F., Yu, W.-N., Rideout, L., Bassous, E. and Le Blanc, A. (1974) Design of Ion-Implanted Small MOSFET’S Dimensions with Very Small Physical Dimensions. IEEE Journal of Solid State Circuits, 9, 257-268. https://doi.org/10.1109/JSSC.1974.1050511
|
[43]
|
Barron, M.B. (1972) Low Level Currents in Insulated Gate Field Effect Transistors. Solid-State Electronics, 15, 293-302. https://doi.org/10.1016/0038-1101(72)90084-6
|
[44]
|
Srikantaiah, J. and DasGupta, A. (2012) Quantum Mechanical Effects in Bulk MOSFETs from a Compact Modeling Perspective: A Review. IETE Technical Review, 29, 3-28. https://doi.org/10.4103/0256-4602.93119
|
[45]
|
Chen, M., Huang, H., Hou, C. and Yang, K. (1998) Back-Gate Bias Enhanced Band-to-Band. IEEE Electron Device Letters, 19, 134-136. https://doi.org/10.1109/55.663538
|
[46]
|
Yang, N., Henson, W.K., Wortman, J.J. and Member, S. (2000) A Comparative Study of Gate Direct Tunneling and Drain Leakage Currents in N-MOSFET’s with Sub-2-nm Gate Oxides. IEEE Transactions on Electron Devices, 47, 1636-1644. https://doi.org/10.1109/16.853042
|
[47]
|
Majkusiak, B. and Badri, M.H. (2000) Semiconductor Thickness and Back-Gate Voltage Effects on the Gate Tunnel Current in the MOS/SOI System with an Ultrathin Oxide. IEEE Transactions on Electron Devices, 47, 2347-2351. https://doi.org/10.1109/16.887019
|
[48]
|
Stadele, M., Tuttle, B.R. and Hess, K. (2009) Tunneling through Ultrathin SiO2 Gate Oxides from Microscopic Models. Journal of Applied Physics, 89, 348-363. https://doi.org/10.1063/1.1330764
|
[49]
|
Larcher, L., Member, S., Paccagnella, A. and Ghidini, G. (2001) Gate Current in Ultrathin MOS Capacitors: A New Model of Tunnel Current. IEEE Transactions on Electron Devices, 48, 271-278. https://doi.org/10.1109/16.902726
|
[50]
|
Yang, K.N., Huang, H.T., Member, S., Chen, M.J., Member, S., Lin, Y.M. and Liang, M.S. (2001) Characterization and Modeling of Edge Direct Tunneling (EDT) Leakage in Ultrathin Gate Oxide MOSFETs. IEEE Transactions on Electron Devices, 48, 1159-1164. https://doi.org/10.1109/16.925242
|
[51]
|
Saheb, Z. and El-Masry, E.I. (2015) Modelling of Direct Tunneling Gate Leakage Current of Floating-Gate CMOS Transistor in sub 100 nm Technologies. Analog Integrated Circuits and Signal Processing, 84, 67-73. https://doi.org/10.1007/s10470-015-0553-8
|
[52]
|
Bowman, K.A., Member, S., Wang, L., Member, S., Tang, X., Meindl, J.D. and Fellow, L. (2001) A Circuit-Level Perspective of the Optimum Gate Oxide Thickness. IEEE Transactions on Electron Devices, 48, 1800-1810. https://doi.org/10.1109/16.936710
|
[53]
|
Choi, C., Member, S., Nam, K., Member, S., Yu, Z. and Member, S. (2001) Impact of Gate Direct Tunneling Current on Circuit Performance: A Simulation Study. IEEE Transactions on Electron Devices, 48, 2823-2829. https://doi.org/10.1109/16.974710
|
[54]
|
Murakami, Y. and Shingyouji, T. (1994) Separation and Analysis of Diffusion and Generation Components of pn Junction Leakage Current in Various Silicon Wafers. Journal of Applied Physics, 75, 3548-3552. https://doi.org/10.1063/1.356091
|
[55]
|
Lee, H. and Hwang, J. (1998) Accurate Extraction of Reverse Leakage Current Components of Shallow Silicided p/sup +/-n Junction for Quarter- and Sub-Quarter-Micron MOSFET’s. IEEE Transactions on Electron Devices, 45, 1848-1850. https://doi.org/10.1109/16.704389
|
[56]
|
Karuppanan, P., Ghosh, S., Khan, K. and Bikki, P. (2017) A Fully Differential Operational Amplifier with Slew Rate Enhancer and Adaptive Bias for Ultra Low Power. Journal of Low Power Electronics, 13, 67-75.
|
[57]
|
Enomoto, T., Oka, Y., Shikano, H., Harada, T. and Science, F. (2002) A Self-Controllable-Voltage-Level (SVL) Circuit for Low-Power, High-Speed CMOS Circuits.
|
[58]
|
Enomoto, T., Oka, Y. and Shikano, H. (2003) A Self-Controllable Voltage Level (SVL) Circuit and Its Low-Power High-Speed CMOS Circuit Applications. IEEE Journal of Solid-State Circuits, 38, 1220-1226. https://doi.org/10.1109/JSSC.2003.813248
|
[59]
|
Deshmukh, J. and Khare, K. (2012) Dynamic SVL and Body Bias for Low Leakage Power and High Performance in CMOS Digital Circuits. International Journal of Electronics, 99, 1717-1728. https://doi.org/10.1080/00207217.2012.692634
|
[60]
|
Narendra, S., Keshavarzi, A., Bloechel, B.A., Borkar, S. and De, V. (2003) Forward Body Bias for Microprocessors in 130-nm Technology Generation and beyond. IEEE Journal of Solid-State Circuits, 38, 696-701. https://doi.org/10.1109/JSSC.2003.810054
|
[61]
|
Nakagome, Y., Horiguchi, M., Kawahara, T. and Itoh, K. (2003) Review and Future Prospects of Low-Voltage RAM Circuits. IBM Journal of Research and Development, 47, 525-552. https://doi.org/10.1147/rd.475.0525
|
[62]
|
Tsuguo, K. and Sakurai, T. (1994) Self-Adjusting Threshold-Voltage Scheme (SATS) for Low Voltage High Speed Operation. Custom Integrated Circuit Conference, San Diego, 1-4 May 1994, 271-274.
|
[63]
|
Kawahara, T., Horiguchi, M., Kawajiri, Y., Kitsukawa, G., Kure, T. and Aoki, M. (1993) Subthreshold Current Reduction for Decoded-Driver by Self-Reverse Biasing. IEEE Journal of Solid-State Circuits, 28, 1136-1144. https://doi.org/10.1109/4.245594
|
[64]
|
Horiguchi, M., Sakata, T. and Itoh, K. (1993) Switched-Source-Impedance CMOS Circuit for Low Standby Subthreshold Current Giga-Scale LSI’s. IEEE Journal of Solid-State Circuits, 28, 1131-1135. https://doi.org/10.1109/4.245593
|
[65]
|
Bikki, P. and Karuppanan, P. (2017) Analysis of Low Power Feedthrough Logic with Leakage Control Technique. Accepted at the 4th International IEEE Conference (ICPCES-2017), MNNIT-Allahabad.
|
[66]
|
Keshavarzi, A., Narendra, S., Borkar, S., Hawkind, C., Roy, K. and De, V. (1999) Technology Scaling Behavior of Optimum Reverse Body Bias for Standby Leakage Power Reduction in CMOS IC’s. International Symposium on Low Power Electronics and Design, San Diego, 16-17 August 1999, 252-254. https://doi.org/10.1145/313817.313937
|
[67]
|
Islam, A. and Hasan, M. (2012) Variability Aware Low Leakage Reliable SRAM Cell Design Technique. Microelectronics Reliability, 52, 1247-1252. https://doi.org/10.1016/j.microrel.2012.01.003
|
[68]
|
Shimazaki, Y., Zlatanovici, R. and Nikoli, B. (2003) A 9uW 50 MHz 32b Adder Using a Self-Adjested Forward Bosy Bias in SOCs. IEEE International ASIC/SOC Conference, Rochester, 25-28 September 2002, 418-419.
|
[69]
|
Kim, C.H.I., Kim, J.J., Mukhopadhyay, S. and Roy, K. (2005) A Forward Body-Biased Low-Leakage SRAM Cache: Device, Circuit and Architecture Considerations. IEEE Transactions on Very Large Scale Integration Systems, 13, 349-357. https://doi.org/10.1109/TVLSI.2004.842903
|
[70]
|
Kim, C.H., Kim, J.-J., Mukhopadhyay, S. and Roy, K. (2003) A Forward Body-Biased-Low-Leakage SRAM Cache: Device and Architecture Considerations. Proceedings of the International Symposium on Low Power Electronics and Design, Seoul, 25-27 August 2003, 6-9. https://doi.org/10.1145/871506.871511
|
[71]
|
Keshavarzi, A., Ma, S., Narendra, S., Bloechel, B., Mistry, K., Ghani, T. and De, V. (2001) Effectiveness of Reverse Body Bias for Leakage Control in Scaled Dual Vt CMOS ICs. Proceedings of the International Symposium on Low Power Electronics and Design, California, 6-7 August 2001, 207-212. https://doi.org/10.1145/383082.383135
|
[72]
|
Kuroda, T. and Sakurai, T. (1996) A 0.9-V, 150-MHz, 10-mW, 4 mm2, 2-D Discrete Cosine Transform Core Processor with Variable Threshold-Voltage (VT) Scheme. IEEE Journal of Solid-State Circuits, 31, 191-201. https://doi.org/10.1109/JSSC.1996.542322
|
[73]
|
Mizuno, H., Ishibashi, K. and Shimura, T. (1999) An 18-uA Standby Current 1.8-V, 200-MHz Microprocessor with Self-Substrate-Biased Data-Retention Mode. IEEE Journal of Solid-State Circuits, 34, 1492-1500. https://doi.org/10.1109/4.799853
|
[74]
|
Zhang, L., Wu, C., Mao, L.-F. and Zheng, J. (2012) Integrated SRAM Compiler with Clamping Diode to Reduce Leakage and Dynamic Power in Nano-CMOS Process. Micro & Nano Letters, 7, 171-173. https://doi.org/10.1049/mnl.2011.0680
|
[75]
|
Shukla, N.K. and Pattanaik, M. (2011) Design and Analysis of a Novel Low-Power SRAM Bit-Cell Structure at Deep-Sub-Micron CMOS Technology for Mobile Multimedia Applications. International Journal of Advanced Computer Science and Applications, 2, 43-49.
|
[76]
|
Neema, V., Chouhan, S.S. and Tokekar, S. (2013) Novel Circuit Technique for Reduction of Leakage Current in Series/Parallel PMOS/NMOS Transistor Stack. IETE Journal of Research, 56, 6-10.
|
[77]
|
Xu, H., Vemuri, R. and Jone, W.-B. (2011) Dynamic Characteristics of Power Gating During Mode Transition. IEEE Transactions on Very Large Scale Integration Systems, 19, 237-249. https://doi.org/10.1109/TVLSI.2009.2033699
|
[78]
|
Kim, K.K., Kim, Y. and Choi, K. (2011) Hybrid CMOS and CNFET Power Gating in Ultralow Voltage Design. IEEE Transactions on Nanotechnology, 10, 1439-1448. https://doi.org/10.1109/TNANO.2011.2168236
|
[79]
|
Powell, M., Falsafi, B., Roy, K. and Vijaykumar, T.N. (2000) Gated-Vdd: A Circuit Technique to Reduce Leakage in Deep-Submicron Cache Memories. ISLPED’00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design, Rapallo, 25-27 July 2000, 90-95. https://doi.org/10.1145/344166.344526
|
[80]
|
Powell, M., Yang, S.H., Falsafi, B., Roy, K. and Vijaykumar, T.N. (2001) Reducing Leakage in a High-Performance Deep-Submicron Instruction Cache. IEEE Transactions on Very Large Scale Integration Systems, 9, 77-89. https://doi.org/10.1109/92.920821
|
[81]
|
Ye, Y., Borkar, S. and De, V. (1998) A New Technique for Standby Leakage Reduction in High-Performance Circuits. 1998 Symposium on VLSI Circuits, Honolulu, 11-13 June 1998, 69-70.
|
[82]
|
Agarwal, A., Li, H. and Roy, K. (2003) A Single-Vt Low-Leakage Gated-Ground Cache for Deep Submicron. IEEE Journal of Solid-State Circuits, 38, 319-328. https://doi.org/10.1109/JSSC.2002.807414
|
[83]
|
Agarwal, A., Li, H. and Roy, K. (2002) DRG-Cache: A Data Retention Gated-Ground Cache for Low Power. Proceedings of the Design Automation Conference, New Orleans, 10-14 June 2002, 473-478. https://doi.org/10.1145/513918.514037
|
[84]
|
Elakkumanan, P., Narasimhan, A. and Sridhar, R. (2003) NC-SRAM—A Low-Leakage Memory Circuit for Ultra Deep Submicron Designs. Proceedings of IEEE International SOC Conference, Portland, 17-20 September 2003, 3-6. https://doi.org/10.1109/soc.2003.1241450
|
[85]
|
Goel, A., Sharma, R.K. and Gupta, A. (2014) Area Efficient Diode and on Transistor Inter-Changeable Power Gating Scheme with Trim Options for SRAM Design in Nano-Complementary Metal Oxide Semiconductor Technology. IET Circuits, Devices & Systems, 8, 100-106. https://doi.org/10.1049/iet-cds.2013.0205
|
[86]
|
Bhavnagarwala, A.J., Kosonocky, S.V., Immediato, M., Knebel, D. and Haen, A.M. (2003) A Pico-Joule Class, 1 GHz, 32 kB 64 b DSP SRAM with Self Reversed Bias. 2003 Symposium on VLSI Circuits, Kyoto, 12-14 June 2003, 251-252.
|
[87]
|
Min, I. and Kanda, K. (2003) Row-by-Row Dynamic Source-Line Voltage Control (RRDSV) Scheme for Two orders of Magnitude Leakage SRAM’s Current Reduction of Sub-1-V-Vdd. 2003 International Symposium on Low Power Electronics and Design, Seoul, 25-27 August 2003, 66-71.
|
[88]
|
Devices, M., Yang, H., Member, S., Hwang, W. and Chuang, C. (2011) Impacts of NBTI/PBTI and Contact Resistance on Power-Gated SRAM with High-. IEEE Transactions on Very Large Scale Integration Systems, 19, 1192-1204. https://doi.org/10.1109/TVLSI.2010.2049038
|
[89]
|
Xie, L., Liu, J. and Wang, Y. (2014) A Low Power CMOS Voltage Reference Generator with Temperature and Process Compensation. Analog Integrated Circuits and Signal Processing, 81, 313-324. https://doi.org/10.1007/s10470-014-0360-7
|
[90]
|
Zhang, K., Bhattacharya, U., Chen, Z., Hamzaoglu, F., Murray, D., Vallepalli, N. and Bohr, M. (2005) SRAM Design on 65-nm CMOS Technology with Dynamic Sleep Transistor for Leakage Reduction. IEEE Journal of Solid-State Circuits, 40, 895-900. https://doi.org/10.1109/JSSC.2004.842846
|
[91]
|
Khellah, M., Somasekhar, D., Ye, Y., Kim, N.S., Howard, J., Ruhl, G. and De, V. (2007) A 256-Kb dual-Vcc SRAM Building Block in 65-nm CMOS Process with Actively Clamped Sleep Transistor. IEEE Journal of Solid-State Circuits, 42, 233-241. https://doi.org/10.1109/JSSC.2006.888357
|
[92]
|
Goel, A., Evans, D., Stephani, R., Reddy, V., Rai, D., Chary, V. and Sathisha, N. (2012) An Area Efficient Diode and on Transistor Interchangeable Power Gating Scheme with Trim Options for Low Power SRAMs. Proceedings of the IEEE International Conference on VLSI Design, Hyderabad, 7-11 January 2012, 80-84. https://doi.org/10.1109/vlsid.2012.50
|
[93]
|
Itoh, K., Nakagome, Y. and Sasaki, K. (1995) Trends in Low-Power RAM Circuit Technologies. Proceedings of the IEEE, 83, 524-543. https://doi.org/10.1109/5.371965
|
[94]
|
Mutoh, S., Douseki, T., Matsuya, Y., Aoki, T., Shigematsu, S. and Yamada, J. (1995) 1-V Power Supply High-Speed Digital Circuit Technology with Multithreshold-Voltage CMOS. IEEE Journal of Solid-State Circuits, 30, 847-854. https://doi.org/10.1109/4.400426
|
[95]
|
Bikki, P. and Karuppanan, P. (2016) Analysis of Low Power and High Performance Multi-Vth Dual Mode Logic Design. Presented at the 11th International IEEE Conference (ICIIS-2016), IIT-Roorkee.
|
[96]
|
Bhavnagarwala, A.J., Tang, X. and Meindl, J.D. (2001) The Impact of Intrinsic Device Fluctuations on CMOS SRAM Cell Stability. IEEE Journal of Solid-State Circuits, 36, 658-665. https://doi.org/10.1109/4.913744
|
[97]
|
Azizi, N., Member, S., Najm, F.N., Moshovos, A. and Member, A. (2003) Low-Leakage Asymmetric-Cell SRAM. IEEE Transactions on Very Large Scale Integration Systems, 11, 701-715. https://doi.org/10.1109/TVLSI.2003.816139
|
[98]
|
Azizi, N. and Moshovos, A. (2002) Asymmetric-Cell Caches: Exploiting Bit Value Biases to Reduce Leakage Power in Deep-Submicron, High-Performance Caches. TR-01-01-02, ECE Dept., Univ. of Toronto, Toronto, 1-14. http://www.eecg.toronto.edu/~moshovos/research/asram-tr.pdf
|
[99]
|
Calhoun, B.H. and Chandrakasan, A.P. (2007) A 256-kb 65-nm Sub-Threshold SRAM Design for Ultra-Low-Voltage Operation. IEEE Journal of Solid-State Circuits, 42, 680-688. https://doi.org/10.1109/JSSC.2006.891726
|
[100]
|
Do, A.T., Nguyen, T.Q., Yeo, K.S. and Kim, T.T. (2013) Sensing Margin Enhancement Techniques for Ultra-Low-Voltage SRAMs Utilizing a Bitline-Boosting Current and Equalized Bitline Leakage. IEEE Transactions on Circuits and Systems II: Express Briefs, 59, 868-872. https://doi.org/10.1109/TCSII.2012.2231014
|
[101]
|
Chen, S.H., Lin, Y.L. and Chao, M.C.T. (2013) Power-Up Sequence Control for MTCMOS Designs. IEEE Transactions on Very Large Scale Integration Systems, 21, 413-423. https://doi.org/10.1109/TVLSI.2012.2187689
|
[102]
|
Kim, T.H., Liu, J. and Kim, C.H. (2009) A Voltage Scalable 0.26 V, 64 kb 8T SRAM with Vmin Lowering Techniques and Deep Sleep Mode. IEEE Journal of Solid-State Circuits, 44, 1785-1795. https://doi.org/10.1109/JSSC.2009.2020201
|
[103]
|
Alvandpour, A., Somasekhar, D., Krishnamurthy, R., De, V., Borkar, S. and Svensson, C. (2003) Bitline Leakage Equalization for Sub-100nm Caches. European Solid- State Circuits Conference, Estoril, 16-18 September 2003, 401-404. https://doi.org/10.1109/esscirc.2003.1257157
|
[104]
|
Wang, B., Nguyen, T.Q., Do, A.T., Zhou, J., Je, M. and Kim, T.T.H. (2015) Design of an Ultra-Low Voltage 9T SRAM with Equalized Bitline Leakage and CAM-Assisted Energy Efficiency Improvement. IEEE Transactions on Circuits and Systems I: Regular Papers, 62, 441-448. https://doi.org/10.1109/TCSI.2014.2360760
|
[105]
|
Teman, A., Pergament, L., Cohen, O. and Fish, A. (2011) A 250 mV 8 kb 40 nm Ultra-Low Power 9T Supply Feedback SRAM (SF-SRAM). IEEE Journal of Solid-State Circuits, 46, 2713-2726. https://doi.org/10.1109/JSSC.2011.2164009
|
[106]
|
Mezhibovsky, J., Teman, A. and Fish, A. (2011) Low Voltage SRAMs and the Scalability of the 9T Supply Feedback SRAM. International System on Chip Conference, Taipei, 26-28 September 2011, 136-141.
|
[107]
|
Kawaguchi, H., Itaka, Y. and Sakurai, T. (1998) Dynamic Leakage Cut-Off Scheme for Low-Voltage SRAM’s. 1998 Symposium on VLSI Circuits, Honolulu, 11-13 June 1998, 140-141. https://doi.org/10.1109/vlsic.1998.688035
|
[108]
|
Kim, C.H. and Roy, K. (2002) Dynamic Vt SRAM: A Leakage Tolerant Cache Memory for Low Voltage Microprocessors. Proceedings of the International Symposium on Low Power Electronics and Design, California, 12-14 August 2002, 251-254. https://doi.org/10.1145/566408.566473
|
[109]
|
Yamauchi, H., Iwata, T., Akamatsu, H., Matsuzawa, A. and Introduction, I. (1996) A 0.8V/100MHz/sub-5mW-Operated Mega-Bit SRAM Cell Architecture with Charge-Recycle Offset-Source Driving (OSD) Scheme. 1996 Symposium on VLSl Circuits, Honolulu, 13-15 June 1996, 126-127.
|
[110]
|
Osada, K., Saitoh, Y., Ibe, E. and Ishibashi, K. (2003) 16.7fA/Cell Tunnel-Leakage-Suppressed 16Mb SRAM for Handling Cosmic-Ray-Induced Multi-Errors. IEEE International Solid-State Circuits Conference, San Franciso, 13 February 2003, 168-169.
|