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Yamauchi, H., Iwata, T., Akamatsu, H., Matsuzawa, A. and Introduction, I. (1996) A 0.8V/100MHz/sub-5mW-Operated Mega-Bit SRAM Cell Architecture with Charge-Recycle Offset-Source Driving (OSD) Scheme. 1996 Symposium on VLSl Circuits, Honolulu, 13-15 June 1996, 126-127.
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