B. Yu and M. L. Bushnell, “Power Grid Analysis of Dynamic Power Cutoff Technology,” Proceedings of International Symposium on Circuits and Systems, New Orleans, 27-30 May 2007, pp. 1393-1396.

has been cited by the following article:

• TITLE: A Parallel Circuit Simulator for Iterative Power Grids Optimization System

  AUTHORS: Taiki Hashizume, Masaya Yoshikawa, Masahiro Fukui

  KEYWORDS: Dedicated Hardware Accelerator; Power Grids Optimization; Parallel Circuit Simulator

  JOURNAL NAME: Circuits and Systems, Vol.3 No.2, April 19, 2012

  ABSTRACT: This paper discusses a high efficient parallel circuit simulator for iterative power grid optimization. The simulator is implemented by FPGA. We focus particularly on the following points: 1) Selection of the analysis method for power grid optimization, the proposed simulator introduces hardware-oriented fixed point arithmetic instead of floating point arithmetic. It accomplishes the high accuracy by selecting appropriate time step of the simulation; 2) The simulator achieves high speed simulation by developing dedicated hardware and adopting parallel processing. Experiments prove that the proposed simulator using 80 MHz FPGA and eight parallel processing achieves 35 times faster simulation than software processing with 2.8 GHz CPU while maintaining almost same accuracy in comparison with SPICE simulation.