TITLE:
A Survey on AI-Augmented Secure RTL Design for Hardware Trojan Prevention
AUTHORS:
Raj Parikh, Khushi Parikh
KEYWORDS:
Logic Locking, Deep Learning in Power Analysis, Siamese Neural Networks (SNNs), Jumping-Knowledge GNNs, Verilog/VHDL Code Analysis
JOURNAL NAME:
Journal of Computer and Communications,
Vol.13 No.4,
April
28,
2025
ABSTRACT: Once, discreet circuit elements, called components, were heaped up on boards inside steel cages using wire-lead technology in just five short years. Fast forward to today, and your computer CPU fits about half an inch square on a chip. Both this constant miniaturization of electronic circuits and the rapid growth in the prevalence of third-party intellectual property parts have made hardware protection more worrisome than ever. Among all these issues, Hardware Trojans (HTs)—which represent corrupted or harmful additions during various design and fabrication stages—pose significant threats to system integrity, privacy of data, and essential infrastructure. This survey gives an in-depth look at how AI can enhance RTL security. It classifies these AI-based techniques into four main categories: GNNs, for instance, can be used to estimate the topology of circuits, extract structural characteristics, and thus find where some corruption has occurred. The SALTY framework applies Jumping-Knowledge GNNs to improve the accuracy location for hardware Trojans. Deep Learning in Side-Channel and Power-Analysis Techniques: Deep learning methods—such as Siamese Neural Networks (SNNs) and Long Short-Term Memory (LSTM) models—have been developed to detect abnormalities brought about by Trojans in power consumption or electromagnetic (EM) radiation, granting non-invasive practices clear security benefits. In conjunction with AI, research teams are now building nearest-neighbor classifiers and decision trees and using reinforcement learning (RL) to recognize occurrences of Trojans inside RTL code. Some research uses Verilog/VHDL conditional statements as features for ML, making it possible for early warning signals to be effectively detected and introducing a proactive security mechanism during the design phase. A step-by-step methodology has evolved for prevention measures such as logic locking and layout hardening, which aims against a splendid prospect within reach. The TroLLoc framework uses logic obfuscation combined with security-aware placement and routing, thus mitigating security exposures post-design.