T. A. Abbasi and M. U. Abbasi, “A Novel FPGA-Based Architecture for Sobel Edge Detection Operator,” International Journal of Electronics, Vol. 94, No. 9, 2007, pp. 889-896. doi:10.1080/00207210701685253

has been cited by the following article:

• TITLE: System Verification of Hardware Optimization Based on Edge Detection

  AUTHORS: Xinwei Niu, Jeffrey Fan

  KEYWORDS: IC; AHB; FPGA; Hardware Optimization; Sobel Edge Detection

  JOURNAL NAME: Circuits and Systems, Vol.4 No.3, June 27, 2013

  ABSTRACT: Nowadays, digital camera based remote controllers are widely used in people’s daily lives. It is known that the edge detection process plays an essential role in remote controlled applications. In this paper, a system verification platform of hardware optimization based on the edge detection is proposed. The Field-Programmable Gate Array (FPGA) validation is an important step in the Integrated Circuit (IC) design workflow. The Sobel edge detection algorithm is chosen and optimized through the FPGA verification platform. Hardware optimization techniques are used to create a high performance, low cost design. The Sobel edge detection operator is designed and mounted through the system Advanced High-performance Bus (AHB). Different FPGA boards are used for evaluation purposes. It is proved that with the proposed hardware optimization method, the hardware design of the Sobel edge detection operator can save 6% of on-chip resources for the Sobel core calculation and 42% for the whole frame calculation.