TITLE:
Design of a New Serializer and Deserializer Architecture for On-Chip SerDes Transceivers
AUTHORS:
Nivedita Jaiswal, Radheshyam Gamad
KEYWORDS:
SerDes Transceiver, Serializer, Deserializer, SoC, Cadence
JOURNAL NAME:
Circuits and Systems,
Vol.6 No.3,
March
27,
2015
ABSTRACT: The
increasing trends in SoCs and SiPs technologies demand integration of large
numbers of buses and metal tracks for interconnections. On-Chip SerDes
Transceiver is a promising solution which can reduce the number of
interconnects and offers remarkable benefits in context with power consumption,
area congestion and crosstalk. This paper reports a design of a new Serializer
and Deserializer architecture for basic functional operations of serialization
and deserialization used in On-Chip SerDes Transceiver. This architecture
employs a design technique which samples input on both edges of clock. The main
advantage of this technique which is input is sampled with lower clock (half
the original rate) and is distributed for the same functional throughput, which
results in power savings in the clock distribution network. This proposed Serializer
and Deserializer architecture is designed using UMC 180 nm CMOS technology and
simulation is done using Cadence Spectre simulator with a supply voltage of 1.8
V. The present design is compared with the earlier published similar works and
improvements are obtained in terms of power consumption and area as shown in
Tables 1-3 respectively. This design also helps the designer for solving
crosstalk issues.