Pooch, U.W. and Wall, J.A. (1993) Discrete Event Simulation. CRC Press, Boca Raton, FL.

has been cited by the following article:

• TITLE: Timed Petri Net Models of Shared-Memory Bus-Based Multiprocessors

  AUTHORS: Wlodek M. Zuberek

  KEYWORDS: Shared-Memory Multiprocessors, Bus-Based Multiprocessors, Timed Petri Nets, Discrete-Event Simulation

  JOURNAL NAME: Journal of Computer and Communications, Vol.6 No.10, October 10, 2018

  ABSTRACT: In shared-memory bus-based multiprocessors, when the number of processors grows, the processors spend an increasing amount of time waiting for access to the bus (and shared memory). This contention reduces the performance of processors and imposes a limitation of the number of processors that can be used efficiently in bus-based systems. Since the multi-processor’s performance depends upon many parameters which affect the performance in different ways, timed Petri nets are used to model shared-memory bus-based multiprocessors at the instruction execution level, and the developed models are used to study how the performance of processors changes with the number of processors in the system. The results illustrate very well the restriction on the number of processors imposed by the shared bus. All performance characteristics presented in this paper are obtained by discrete-event simulation of Petri net models.