A Co-verification Method Based on TWCNP-OS for Two-way Cable Network SOC


Co-verification is the key step of software and hardware codesign on SOC. This paper presents a hw/sw co-verification methodology based on TWCNP-OS, a Linux-based operating system designed for FPGA-based platform of two-way cable network (TWCNP) SOC. By implementing HAL (hardware Abstraction level) specially, which is the communications interface between hardware and software, we offer a homogeneous Linux interface for both software and hardware processes. Hardware processes inherit the same level of service from kernel, as typical Linux software processes by HAL. The familiar and language independent Linux kernel interface facilitates easy design reuse and rapid application development. The hw/sw Architecture of TWCNP and design flow of TWCNP-OS are presented on detail. A software and hardware co-verification method using TWCNP-OS is proposed, through the integrated using of Godson-I test board and TWCNP, which realizes the combination of design and verification. It is not a replacement of the co-verification with generic RTOS modeling, but is complementary to them. Performance analysis of our current implementation and our experience with developing this system based on TWCNP-OS will be presented. Most importantly, since the introduction of TWCNP-OS to our FPGA-based platform, we have observed increased productivity among high-level application developers who have little experience in FPGA application design.

Share and Cite:

C. LI, X. ZHANG, Y. WAN and Q. WANG, "A Co-verification Method Based on TWCNP-OS for Two-way Cable Network SOC," International Journal of Communications, Network and System Sciences, Vol. 1 No. 2, 2008, pp. 199-206. doi: 10.4236/ijcns.2008.12024.

Conflicts of Interest

The authors declare no conflicts of interest.


[1] N. Ohba and K. Takano, “An SoC design methodology using FPGAs and embedded microprocessors,” Proceedings of the 41st annual conference on Design automation, San Diego, CA, USA, June 07–11, 2004.
[2] Habibi and S. Tahar, “Design and verification of SystemC transaction-level models,” IEEE Trans. VLSI Syst., 14(1): pp. 57–68, January 2006.
[3] H. So, A. Tkachenko, and R. Brodersen, “A Unified Hardware/Software Runtime Environment for FPGA-Based Reconfigurable Computers using BORPH,” CODES+ISSS, 2006.
[4] D. Atienza, P.G. Del Valle, G. Paci, et al., “A fast HW/SW FPGA-based thermal emulation framework for multi-processor system-on-chip,” Proceedings of the 43rd annual conference on Design automation, San Francisco, CA, USA, July 24–28, 2006.
[5] Y. Nakamura, K. Hosokawa, I. Kuroda, K. et al., “A fast hardware/software co-verification method for system-on-a-chip by using a C/C++ simulator and FPGA emulator with shared register communication,” Proceedings of the 41st Design Automation Conference (DAC' 04), San Diego, Calif., USA, pp. 299–304, June 2004.
[6] D. Desmet, D. Verkest, and H. De Man, “Operating system based software generation for systems-on-chip,” Proceedings of Design Automation Conference (DAC), 2000.
[7] A. Gerstlauer, H. Yu, and D. Gajski, “RTOS modeling for system level design,” Proceedings of Design Automation and Test in Europe (DATE), Embedded Software Forum, 2003.
[8] SpecC Technology Open Consortium, http://www.specc.org/.
[9] H. Tomiyama, Y. Cao, and K. Murakami, “Modeling fixedpriority preemptive multi-task systems in SpecC,” Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), 2001.
[10] Y. Yi, D. Kim, and S. Ha, “Virtual synchronization technique with OS modeling for fast and time-accurate cosimulation,” Proceedings of International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), 2003.
[11] F. Herrera, H. Posadas, P. Sanchez, and E. Villar, “Systematic embedded software generation from SystemC,” Proceedings of Design Automation and Test in Europe (DATE), Embedded Software Forum, 2003.
[12] S. Honda, T. Wakabayashi, H. Tomiyama, et al., “RTOS-centric hardware/software cosimulator for embedded system design,” Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, Stockholm, Sweden, September 08–10, 2004.
[13] ITRON, http://www.assoc.tron.org/itron/.
[14] http://www.linux-mips.org/wiki/PMON.
[15] http://cross-lfs.org/view/svn/mips/index.html.
[16] http://linux.junsun.net/porting-howto/.
[17] Mentor Graphics Corporation, http://www.mentor.com.
[18] C. Wang, X.G. Xue, et al., “FPGA/CPLD Design TOOL- Specification for Xilinx ISE 5.X,” Posts and Telecom Press, 2003.
[19] S. Yoo, I. Bacivarov, A. Bouchima, et al., “Building fast and accurate SW simulation models based on hardware abstraction layer and simulation environment abstraction layer,” Proceedings of the Design, Automation and Test in Europe (DATE' 03), Munich, Germany, pp. 500–506, March 3–7, 2003.

Copyright © 2024 by authors and Scientific Research Publishing Inc.

Creative Commons License

This work and the related PDF file are licensed under a Creative Commons Attribution 4.0 International License.