A Scalable Model of the Substrate Network in Deep n-Well RF MOSFETs with Multiple Fingers

Jun Liu, Marissa Condon
DOI: 10.4236/cs.2011.22014                

Abstract

A novel scalable model of substrate components for deep n-well (DNW) RF MOSFETs with different number of fingers is presented for the first time. The test structure developed in [1] is employed to directly access the characteristics of the substrate to extract the different substrate components. A methodology is developed to directly extract the parameters for the substrate network from the measured data. By using the measured two-port data of a set of nMOSFETs with different number of fingers, with the DNW in grounded and float configuration, respectively, the parameters of the scalable substrate model are obtained. The method and the substrate model are further verified and validated by matching the measured and simulated output admittances. Excellent agreement up to 40 GHz for configurations in common-source has been achieved.

Keywords

Deep N-Well (DNW), RF Mosfets, Substrate Network, Scalable Model

Conflicts of Interest

The authors declare no conflicts of interest.

References

[1]	J. Liu, L. L. Sun, L. L. Lou, H. Wang and C. McCorkell, “A Simple Test Structure for Directly Extracting Substrate Network Components in Deep N-Well RF CMOS Modeling,” IEEE Electron Device Letters, Vol. 30, No. 11, 2009, pp. 1200-1202.
[2]	J. G. Su, H. M. Hsu, S. C. Wong, C. Y. Chang, T. Y. Huang and J. Y. C. Sun, “Improving the RF Per-formance of 0.18-um CMOS with Deep N-Well Implantation,” IEEE Electron Device Letters, Vol. 22, No. 10, 2001, pp. 481-483.
[3]	K. W. Chew, J. Zhang, K. Shao, W. B. Loh, and S. F. Chu, “Impact of Deep N-Well Implantation on Substrate Noise Coupling and RF Transistor Performance for Sys-tems-on-a-Chip Integration,” Proceeding of the 32nd European Solid-State Device Research Conference, Bologna, 24-26 Sep-tember 2002, pp. 251-254.
[4]	D. Kosaka, M. Nagata, Y. Hiraoka, I. Imanishi, M. Maeda, Y. Murasaka and A. Iwata, “Isolation Strategy Against Substrate Coupling in CMOS Mixed-Signal/RF Circuits,” Symposium on VLSI Circuits Digest of Technical Papers, Kyoto, 16-18 June 2005, pp. 276-279.
[5]	J. Kang, D. Yu, Y. Yang and B. Kim, “Highly Linear 0.18-m CMOS Power Amplifier with Deep-N-Well Structure,” IEEE Journal of Solid-State Circuits, Vol. 41, No. 5, 2006, pp. 1073-1080. doi:10.1109/JSSC.2006.874059
[6]	S. F. W. M. Hatta and N. Soin, “Performance of the Forward-Biased RF LNA with Deep N-Well NMOS Transistor,” Proceeding of International Con-ference on Semiconductor Electronics, Johor Bahru, 25-27 November 2008, pp. 465-469.
[7]	J. Han and H. Shin, “A Scalable Model for the Substrate Resistance in Multi-Finger RF MOSFETs,” IEEE MTT-S International Microwave Symposium Digest, Philadelphia, 8-13 June 2003, pp. 2105-2108.
[8]	Y. Cheng and M. Matloubian, “Parameter Extraction of Accurate and Scaleable Substrate Resistance Components in RF MOS-FETs,” IEEE Electron Device Letters, Vol. 23, No. 4, 2002, pp. 221-223. doi:10.1109/55.992845
[9]	N. Srirattana, D. Heo, H. M. Park, A. Raghavan, P. E. Allen and J. Laskar, “A New Analytical Scalable Substrate Network Model for RF MOS-FETs,” IEEE MTT-S Microwave Symposium Digest, Fort Worth, 6-11 June 2004, pp. 699-702.
[10]	I. M. Kang, S. J. Jung, T. H. Choi, H. W. Lee, G. Jo, Y. K. Kim, H. G. Kim and K. M. Choi, “Scalable Model of Substrate Resistance Components in RF MOSFETs with Bar-Type Body Contact Considered Layout Dimensions,” IEEE Electron Device Letters, Vol. 30, No. 4, 2009, pp. 404-406. doi:10.1109/LED.2009.2014085
[11]	S. P. Voinigescu, M. Tazlauanu, P. C. Ho and M. T. Yang, “Direct Extraction Methodology for Geometry-Scalable RF-CMOS Models,” International Conference on Microelectronic Test Structures, Awaji, 22-25 March 2004, pp. 235-240.
[12]	S. P. Kao, C. Y. Lee, C. Y. Wang, J. D.-S. Deng, C. C. Chang and C. H. Kao, “An Analytical Extraction Method for Scalable Substrate Resistance Model in RF MOSFETs,” 2007 International Semiconductor Device Research Symposium, College Park, 12-14 December 2007, pp. 1-2.
[13]	B. Parvais, S. Hu, M. Dehan, A. Mercha and S. Decoutere, “An Analytical Extraction Method for Scalable Substrate Resistance Model in RF MOSFETs,” Custom Integrated Circuits Conference, San Jose, 16-19 September 2007, pp. 503-506.
[14]	Y. Cheng, M. J. Deen and C. H. Chen, “MOSFET Modeling for RF IC Design,” IEEE Transactions on Electron Devices, Vol. 52, No. 7, 2005, pp. 1286-1303. doi:10.1109/TED.2005.850656
[15]	M. M. Tabrizi, E. Fathi, M. Fathipour and N. Masoumi, “Extracting of Substrate Network Resistances in RF CMOS Transistors,” Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, Atlanta, 8-10 September 2004, pp. 219-222.
[16]	J. Han, M. Je and H. Shin, “A Simple and Accurate Method for Extracting Substrate Resistance of RF MOSFETs,” IEEE Electron Device Letters, Vol. 23, No. 7, 2002, pp. 434-436.
[17]	Y. S. Lin, “An Analysis of Small-Signal Source-Body Resistance Effect on RF MOSFET for Low-Cost System-on-Chip (SoC) Applications,” IEEE Transactions on Electron Devices, Vol. 52, No. 7, 2005, pp. 1442-1451. doi:10.1109/TED.2005.850691
[18]	S. C. Rustagi, L. Huailin, S. Jinglin and Z. X. Yong, “BSIM3 RF Models for MOS Transistors: A Novel Technique for Substrate Network Extraction,” Proceeding of IEEE International Con-ference on Microelectronic Test Structures, Monterey, 17-20 March 2003, pp. 118-123.
[19]	U. Mahalingam, S. C. Rustagi and G. S. Samudra, “Direct Extraction of Substrate Network Parameters for RF MOSFET Modeling Using a Simple Test Structure,” IEEE Device Letters, Vol. 27, No. 2, 2006, pp. 130-132. doi:10.1109/LED.2005.863132