Reliability of High Speed Ultra Low Voltage Differential CMOS Logic

Omid Mirmotahari^1*, Yngvar Berg²

¹Nanoelectronics System Group, Department of Informatics, Universisty of Oslo, Oslo, Norway.
²Department of Micro- and Nanosystems Technology, Buskerud & Vestfold University College, Horten, Norway.

DOI: 10.4236/cs.2015.65013                

Abstract

In this paper, we present a solution to the ultra low voltage inverter by adding a keeper transistor in order to make the semi-floating-gate more stable and to reduce the current dissipation. Moreover, we also present a differential ULV inverter and elaborate on the reliability and fault tolerance of the gate. The differential ULV gate compared to both a former ULV gate and standard CMOS are given. The results are obtained through Monte-Carlo simulations.

Keywords

CMOS, Differential, Floating-Gate, Semi-Floating-Gate, Keeper, Recharge, Ultra Low Voltage, High Speed, Monte-Carlo, Cadence, STM, 90 nm

Conflicts of Interest

The authors declare no conflicts of interest.

References

[1]	Verma, N., Kwong, J. and Chandrakasan, A. (1995) Nanometer MOSFET Variation in Minimum Energy Subthreshold Circuits. IEEE Transactions on Electron Devices, 55, 847-854.
[2]	Chandrakasan, A.P., Sheng, S. and Brodersen, R.W. (1992) Low-Power CMOS Digital Design. IEEE Journal of Solid-State Circuits, 27, 473-484.
[3]	Burr, J.B. and Peterson, A.M. (1991) Ultra Low Power CMOS Technology. NASA VLSI Design Symposium, Idaho, 30-31 October 1991, 4.2.1-4.2.13.
[4]	Burr, J.B. and Shott, J. (1994) A 200 mV Self-Testing Encoder/Decoder Using Stanford Ultra Low-Power CMOS. IEEE Solid-State Circuits Conference (ISSCC), San Francisco, 16-18 February 1994, 84-85. http://dx.doi.org/10.1109/ISSCC.1994.344717
[5]	Usami, K. and Horowitz, M. (1995) Clustered Voltage Scaling Technique for Low-Power Design. Proceedings of the 1995 International Symposium on Low Power, Dana Point, 23-26 April 1995, 3-8. http://dx.doi.org/10.1145/224081.224083
[6]	Berg, Y., Wisland, D.T. and Lande, T.S. (1999) Ultra Low-Voltage/Low-Power Digital Oating-Gate Circuits. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 46, 930-936.
[7]	Berg, Y., Mirmotahari, O., Norseng, P.A. and Aunet, S. (2006) Ultra Low Voltage CMOS Gates. IEEE International Conference on Electronics, Circuits and Systems (ICECS), Nice, 10-13 December 2006, 818-821.
[8]	Mirmotahari, O. and Berg, Y. (2009) Digital Ultra Low Voltage High Speed Logic. Proceedings of the International MultiConference of Engineers and Computer Scientists, Hong Kong, 18-20 March 2009, 1-1.
[9]	Berg, Y., Mirmotahari, O., Lomsdalen, J. and Aunet, S. (2008) High Speed Ultra Low Voltage CMOS Inverter. IEEE Computer Society Annual Symposium on VLSI, Montpellier, 7-9April 2008, 122-127.
[10]	Mirmotahari, O. and Berg, Y. (2008) Low Voltage Design against Power Analysis Attacks. IEEE International Symposium on Electronic Design, Test and Applications (DELTA), Hong Kong, 23-25 January 2008, 545-549.
[11]	Mirmotahari, O. and Berg, Y. (2008) Ultra Low Voltage High Speed Differential CMOS Inverter. IEEE PATMOS LNCS, 10-12 September 2008, Lisbon, Portugal, 1-1.