Design of Ultra-Low Power PMOS and NMOS for Nano Scale VLSI Circuits

Ashok Babu Ch^1*, J. V. R. Ravindra², K. Lalkishore³

¹Department of Electronics and Communication Engineering, SVIT, Sec-Bad, India.
²Department of Electronics and Communication Engineering, Vardhaman College of Engineering, Hyderabad, India.
³Jawaharalal Nehru Technological University, Anantapur, India.

DOI: 10.4236/cs.2015.63007                

Abstract

CMOS devices play a major role in most of the digital design, since CMOS devices have larger density and consume less power. The integrated circuit performance mostly depends on the basic devices and its scaling methods, but in conventional CMOS devices in ultra deep submicron technology, leakage power becomes the major portion apart of dynamic power. The demerits of the conventional CMOS is less speed and, more leakage, for any digital design PDP is the figure of merit which can be used to determine energy consumed per switching event, hence we designed a NOVEL NMOS and PMOS which has superior performance than conventional PMOS and NMOS, the design and performance checked at 90 nm, 180 nm and 45 nm technology and calculate the performance values.

Keywords

Power Delay Product, Average Power, Static Power, Delay, Dynamic Threshold CMOS

Conflicts of Interest

The authors declare no conflicts of interest.

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