Designing a Full Adder Circuit Based on Quasi-Floating Gate

DOI: 10.4236/epe.2013.53B012   PDF   HTML     5,385 Downloads   6,468 Views   Citations

Abstract

Since in designing the full adder circuits, full adders have been generally taken into account, so as in this paper it has been attempted to represent a full adder cell with a significant efficiency of power, speed and leakage current levels. For this objective, a comparison between five full adder circuits has been provided. Applying floating gate technology and refresh circuits in the full adder cell lead to the reduction of leakage current on the gate node. The simulations were accomplished in this paper, through HSPICE software and 65 nm CMOS technology. The simulation results indicate the considerable efficiency of power consumption, speed and leakage current in the full adder cell rather than other cells.

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S. Bonakdarpour and F. Razaghian, "Designing a Full Adder Circuit Based on Quasi-Floating Gate," Energy and Power Engineering, Vol. 5 No. 3B, 2013, pp. 57-63. doi: 10.4236/epe.2013.53B012.

Conflicts of Interest

The authors declare no conflicts of interest.

References

[1] A. Bellaouar and I. Mohammad and Elmasary, “Low Power Digital VLSI Design, Circuits and Systems,” Kluwer Academic Publishers, Norwell, Massachusetts, USA, 1998.
[2] J. T. Kao and A. P. Chandrakasan, “Dual-threshold Techniques for Low Power Digital Circuits,” IEEE Journal of Solid State Circuits, Vol. 35, No. 7, 2000, pp.1009-1018. doi:10.1109/4.848210
[3] J. Alfredsson, S. Aunet and B. Oelmann, “Basic Speed and Powerproperties of Digital Floating Gate Circuits Operating in Subthreshold,”Proceeding of IFIP International Conference on Very Large Scale Integration, IFIP VLSI-SOC 2005, Australia , 2005.
[4] J. Alfredsson and B. Oelmann, “Influence of Refresh Circuits Connected to Low Power Digital Quasi–floating Gate Designs,”IEEE International Conference on Electronics, Circuits and Systems, Vol. 1-3, 2006, pp. 1296-1299.
[5] E. R. Villages, “Low Power and Low Voltage Circuit Design with the FGMOS Transistor,” the Institute of Engineering and Technology, London, 2006.
[6] K. A. Townsend, J. W. Haslett and K. Iniewski, “Design and Optimization of Low Voltage Quasi floating Gate Digital Circuits,” Proceeding of 9th international database engineering and application symposium 2005, IDEAS 05, 2005.
[7] A. Bellaouar, I. Mohammad and Elmasary, “Low Power Digital VLSI Design,” 1998.
[8] F. Razaghian and S. Bonakdarpour, “Reducing the Leakage Current and PDP in the Quasi-Floating Gate Circuits,” Spring World Congress on Engineering and Technology (SCET2012), Xi'an, China, Vol. 1, 2012, pp. 602-605.
[9] J. Alfredsson and B. Oelmann, "Influence of Refresh Circuits Connected to Low Power Digital Quasi-Floating Gate Designs," IEEE International Conference on Electronics, Circuits and Systems, Vol. 1-3, 2006, pp. 1296-1299.
[10] E. S. Sinencio, "Floating Gate Techniques and Applications," Analog and Mixed-Signal Center TAMU, 2010.
[11] E. R. Villegas,”Low Power and Low Voltage Circuit Design with the FGMOS Transistor,” The Institution of Engineering and Technology, London.
[12] K. Navi and K. H. Omid, “Low Power and High Performance 1-Bit CMOS Full-adder Cell,” Journal of Computers, Vol. 3, No. 2, 2008.
[13] A. Sayed and H. Al. Assa, “Survey and Evaluation of Low-power Full-adder Cells,” in Proceedings of ESA /VLSI, 2004, pp. 332-338.
[14] R. F. Mirzaee, Mohammad, H. M. Hussein and N. Keivan, “High Speed NP-CMOS and Multi-output Dynamic Full Adder Cells,” International Journal of Electrical, Computer and Systems Engineering, Vol. 4, No. 4, 2010.
[15] K. Navi, V. Foroutan, M. R. Azghadi, M. Maeen, M. Ebrahimpour, M. Kaveh and O. Kavehei, “A Novel Low-power Full Adder Cell with New Technique in Designing Logical Gates Based on Static CMOS Inverter,” Microelectronics Journal, Vol. 40, No.10, 2009.
[16] R. Shalem, K. J. Lizy and J. Eugene, “A Novel Low Power Energy Recovery Full Adder Cell,” in Proceedings of Great Lakes Symposium on VLSI, 1999, pp. 380-388.
[17] D. Radhakrishnan, “Low-voltage Low-power CMOS Full Adder,”Proceeding IEE Circuits Devices and Systems, Vol. 148, No. 1, 2001, pp.19-24.

  
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