Author(s)

Xinjie Wang^*, Tadeusz Kwasniewski

Department of Electronics, Carleton University, Ottawa, Canada.

Static phase offset (SPO) in conventional multiplying delay-locked loops (MDLLs) dramatically degrades the deterministic jitter performance. To overcome the issue, this paper presents a new SPO reduction technique for MDLLs. The technique is based on the observation that the SPO of MDLL is mainly caused by the non-idealities on charge pump (e.g. sink and source current mismatch), and control line (e.g. gate leakage of loop filter and voltage controlled delay line (VCDL) control circuit). With a high gain stage inserting between phase detector/phase frequency detector (PD/PFD) and charge pump, the equivalent SPO has been decreased by a factor equal to the gain of the gain stage. The effectiveness of the proposed technique is validated by a Simulink model of MDLL. The equivalent SPO is measured by the power level of reference spur.

Static Phase Offset, Multiplying Delay-Locked Loop, Deterministic Jitter, Reference Spur, PLL

Wang, X. and Kwasniewski, T. (2015) A Static Phase Offset Reduction Technique for Multiplying Delay-Locked Loop. Circuits and Systems, 6, 13-19. doi: 10.4236/cs.2015.61002.