Author(s)

Hassen Loukil, Imen Werda, Nouri Masmoudi, Ahmed Ben Atitallah, Patrice Kadionik

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In this paper, we propose novel hardware architecture for intra 16 × 16 module for the macroblock engine of a new video coding standard H.264. To reduce the cycle of intra prediction 16 × 16, transform/quantization, and inverse quantization/inverse transform of H.264, an advanced method for different operation is proposed. This architecture can process one macroblock in 208 cycles for all cases of macroblock type by processing 4 × 4 Hadamard transform and quantization during 16 × 16 prediction. This module was designed using VHDL Hardware Description Language (HDL) and works with a 160 MHz frequency using ALTERA NIOS-II development board with Stratix II EP2S60F1020C3 FPGA. The system also includes software running on an NIOS-II processor in order to implementing the pre-processing and the post-processing functions. Finally, the execution time of our HW solution is decreased by 26% when compared with the previous work.

Nios H.264, FPGA, Intra 16 × 16, NIOS-II, SOPC Design

Loukil, H. , Werda, I. , Masmoudi, N. , Ben Atitallah, A. and Kadionik, P. (2010) FPGA Design of an Intra 16 × 16 Module for H.264/AVC Video Encoder. Circuits and Systems, 1, 18-29. doi: 10.4236/cs.2010.11004.