Author(s)

R. Gandhi Raj¹, S. Palani², H. Habeebullah Sait¹

¹Department of Electrical and Electronics Engineering, Anna University, BIT Campus, Tiruchirappalli, India.
²Department of Electronics and Communication Engineering, Sudharsan Engineering College, Pudukottai, India.

This paper presents a new transformer based multilevel inverter, with a novel pulse width modulation scheme to achieve seven-level inverter output voltage. The proposed inverter switching pattern consists of three fundamental frequency sinusoidal reference signals with an offset value, and one high frequency triangular carrier signal. This switching scheme has been implemented using an 8-bit Xilinx SPARTAN-3E field programmable gate array based controller. In addition, the state space model of the proposed inverter is developed. The significant features of the proposed topology are: reduction of the power switch count and the gate drive power supply unit, the provision of a galvanic isolation between load and sources by a centre tap transformer. An exhaustive comparison has been made of the existing multilevel inverter topologies and the proposed topology. The performances of the proposed topology with resistive, resistive-inductive loads are simulated in a MATLAB environment and validated experimentally on a laboratory prototype.

Centre Tap Transformer, Field Programmable Gate Array (FPGA), Multilevel Inverter (MLI), Pulse Width Modulation (PWM), State Space Model

Raj, R. , Palani, S. and Sait, H. (2016) State Space Modeling and Implementation of a New Transformer Based Multilevel Inverter Topology with Reduced Switch Count. Circuits and Systems, 7, 446-463. doi: 10.4236/cs.2016.74038.