World Journal of Nano Science and Engineering

Volume 3, Issue 1 (March 2013)

ISSN Print: 2161-4954   ISSN Online: 2161-4962

Google-based Impact Factor: 0.83  Citations  

Threshold Voltage Sensitivity to Metal Gate Work-Function Based Performance Evaluation of Double-Gate n-FinFET Structures for LSTP Technology

HTML  XML Download Download as PDF (Size: 608KB)  PP. 17-22  
DOI: 10.4236/wjnse.2013.31003    11,367 Downloads   16,670 Views  Citations

ABSTRACT

This paper investigates the threshold voltage sensitivity to metal gate work-function for n-channel double gate fin field-effect transistor (FinFET) structures and evaluates the short channel performance of the device using threshold voltage dependence on metal gate work-function analysis. We carried out the study for a double gate n-channel fin field-effect transistor (n-FinFET) with parameters as per the projection report of International Technology Roadmap for Semiconductors, ITRS-2011 for low standby power (LSTP) 20 nm gate length technology node. In the present study device simulation have been carried out using PADRE simulator from MuGFET, which is based on the drift-diffusion theory. Our results show the accuracy and validity of classical drift-diffusion simulation results for transistor structures with lateral dimensions 10nm and above. The subthreshold behavior of device improves with increased metal gate work-function. The results also show that a higher gate work-function (≥5 eV) can fulfill the tolerable off-current as projected in ITRS 2011 report. The SCE in FinFET can reasonably be controlled and improved by proper adjustment of the metal gate work-function. DIBL is reduced with the increase in gate work function.

Share and Cite:

Mustafa, M. , Bhat, T. and Beigh, M. (2013) Threshold Voltage Sensitivity to Metal Gate Work-Function Based Performance Evaluation of Double-Gate n-FinFET Structures for LSTP Technology. World Journal of Nano Science and Engineering, 3, 17-22. doi: 10.4236/wjnse.2013.31003.

Cited by

[1] Top gate engineering of field-effect transistors based on wafer-scale two-dimensional semiconductors
Journal of Materials …, 2022
[2] Engineering Top Gate Stack for Wafer-Scale Integrated Circuit Fabrication Based on Two-Dimensional Semiconductors
… Applied Materials & …, 2022
[3] Mathematical Modeling and Performance Evaluation of 3D Ferroelectric Negative Capacitance FinFET
… and Simulation in …, 2022
[4] Exploring XOR-based Full Adders and decoupling cells to variability mitigation at FinFET technology
Integration, 2022
[5] A Pragmatic Quaternary FPGA Implemented with Floating Gate Memories
2021
[6] High-Performance Organic Field-Effect Transistors Gated by Imidazolium-Based Ionic Liquids
2021
[7] Modeling, estimation and reduction of total leakage in scaled CMOS logic circuits
2021
[8] A Practical Quaternary FPGA Architecture Using Floating Gate Memories
2020
[9] Characterization of various FinFET based 6T SRAM cell configurations in light of radiation effect
2020
[10] GaN Nanotube FET With Embedded Gate for High Performance, Low Power Applications
2020
[11] Impact of High-K Gate Dielectric and Work functions Variation on Electrical Characteristics of VeSFET
2020
[12] Multi-Level Design Influences on Robustness Evaluation of 7nm FinFET Technology
2019
[13] Impact of stress effect on triple material gate step-FinFET with DC and AC analysis
2019
[14] Analytical modeling of threshold voltage and subthreshold swing in Si/Ge heterojunction FinFET
2019
[15] Transistor gate metal with laterally graduated work function
2019
[16] Leakage Suppression Approaches in Bulk FinFETs
2019
[17] Variability analysis of FinFET AC/RF performances through efficient physics-based simulations for the optimization of RF CMOS stages
Dissertation, 2018
[18] Device characterization based on stressor, geometric and process design considerations of fet technology/Nurul Aida Farhana Othman
2018
[19] Analytical model of surface potential and threshold voltage in gate-drain overlap FinFET
Microelectronics Journal, 2018
[20] Design and Analysis of Pressure Sensor Based on MEMS Cantilever Structure and Pocket Doped DG-TFET
Journal of Nanoelectronics and Optoelectronics, 2018
[21] Analysis of 6 T SRAM cell in sub-45 nm CMOS and FinFET technologies
Microelectronics Reliability, 2018
[22] Tunable work function in Junctionless Tunnel FETs for performance enhancement
Australian Journal of Electrical and Electronics Engineering, 2018
[23] Degradation analysis based on design considerations of advanced-process MOSFET/Ainul Fatin Muhammad Alimin
2018
[24] Preparation of rare earth CeO 2 thin films using metal organic decomposition method for metal-oxide–semiconductor capacitors
2017
[25] Impacts of fin width scaling on the electrical characteristics of 10-nm FinFET at different metal gate work function
2017
[26] TCAD based performance analysis of junctionless cylindrical double gate all around FET up to 5nm technology node
2017
[27] Investigate Sub-Threshold Performance Measures of Cylindrical Gate All Around MOSFET at Sub-Nanometer Regime
i-Manager's Journal on Embedded Systems, 2017
[28] Design of Triple Gate for Sub threshold Low Power applications
2017
[29] Preparation of rare earth CeO2 thin films using metal organic decomposition method for metal-oxide–semiconductor capacitors
Journal of Materials Science: Materials in Electronics, 2017
[30] Design of Triple Gate for Sub-threshold Low Power Applications.
Defence Science Journal, 2017
[31] TCAD Simulation Analysis of Tri-Gate SOI FINFET and Its Application
2017
[32] Fin and Gate Geometry Effects on the Junctionless Field Effect Transistors
Journal of Nanoelectronics and Optoelectronics, 2017
[33] Junctionless GAA nanowire transistor: Towards circuit application
2016
[34] Reduction of GIDL Using Dual Work-Function Metal Gate in DRAM
2016
[35] Study and Simulation of a Nanoscale Structure of a Multi-gate MOS Transistor
2016
[36] Performance evaluation of FinFET and Nanowire at different technology nodes
2015
[37] Investigation of short channel effects in Bulk MOSFET and SOI FinFET at 20nm node technology
2015
[38] Performance evaluation of novel low leakage Double-gate FinFET device at sub-22nm with LaAlO3 high-k gate oxide and TiN metal gate using quantum …
2014
[39] Evaluating the impact of environment and physical variability on the ION current of 20nm FinFET devices
2014
[40] Work Function and Gate Length Effect On Electrical Characteristics Of n-FinFET in 3D Using ATLAS SILVACO
2014
[41] Reavaliando Falhas Stuck-Open em nanotecnologias sub-45nm: Uma análise comportamental
Iberchip 2014, 2014
[42] Predictive evaluation of electrical characteristics of sub-22nm FinFET technologies under device geometry variations
Microelectronics Reliability. Elsevier, 2014
[43] Performance evaluation of novel low leakage Double-gate FinFET device at sub-22nm with LaAlO 3 high-k gate oxide and TiN metal g
Electronics and Communication Systems (ICECS), 2014 International Conference on. IEEE, 2014
[44] Evaluating the impact of environment and physical variability on the I ON current of 20nm FinFET devices
Power and Timing Modeling, Optimization and Simulation (PATMOS), 2014 24th International Workshop on, 2014
[45] Performance evaluation of novel low leakage Double-gate FinFET device at sub-22nm with LaAlO3 high-k gate oxide and TiN metal gate using quantum modeling
2014
[46] Predictive evaluation of electrical characteristics of sub-22 nm FinFET technologies under device geometry variations
Microelectronics Reliability, 2014
[47] An analysis of FinFET devices under environment and process variability
2013
[48] SUITABILITY OF HIGH-k GATE DIELECTRICS ON THE DEVICE PERFORMANCE AND SCALABILITY OF NANOSCALE DOUBLE GATE FINFETS WITH QUANTUM MODELING: A SIMULATION STUDY
Journal of Electron Devices, 2013
[49] Suitability of High-k gate dielectrics on the device performance and scalability of nanoscale double gate FinFETs with quantum modeling: a simulation …
J. Electron Devices France, 2013

Copyright © 2024 by authors and Scientific Research Publishing Inc.

Creative Commons License

This work and the related PDF file are licensed under a Creative Commons Attribution 4.0 International License.