Design of a Low Power Low-Noise Amplifier with Improved Gain/Noise Ratio ()
ABSTRACT
This
work details the development of a broad-spectrum LNA (Low Noise Amplifier)
circuit using a 65 nm CMOS technology. The design incorporates an inductive degeneracy
circuit, employing a theoretical approach to enhance gain, minimize noise
levels, and uphold low power consumption. The progression includes a shift to a
cascode structure to further refine LNA parameters. Ultimately, with a 1.8 V bias,
the achieved performance showcases a gain-to-noise figure ratio of 16 dB/0.5
dB, an IIP3 linearity at 5.1 dBm, and a power consumption of 3 mW. This
architecture is adept at operating across a wide frequency band spanning from
0.5 GHz to 6 GHz, rendering it applicable in diverse RF scenarios.
Share and Cite:
Mahmou, R. and Faitah, K. (2024) Design of a Low Power Low-Noise Amplifier with Improved Gain/Noise Ratio.
World Journal of Engineering and Technology,
12, 80-91. doi:
10.4236/wjet.2024.121005.
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