In this paper, a low-noise charge-sensitive preamplifier (CSA) is designed based on passivation ion implanted planar silicon (PIPS: The Passivated Implanted Planar Silicon) detectors. This charge-sensitive preamplifier uses Junction Field-Effect Transistor (JFET) as the first stage of the amplifier. In order to maximize the signal-to-noise ratio and consider the resistance-capacitance matching problem, according to different PIPS detector junction capacitances, different numbers of junction field effect transistors are matched in parallel in the first stage. Slotting technology is used at the feedback end to reduce the influence of the parasitic capacitance of the PCB board on the feedback, and the feedback capacitor resistance is adjusted to achieve the best signal-to-noise ratio. Experimental test results show that the charge-sensitive preamplifier can achieve a signal-to-noise ratio greater than 100 at room temperature, the output signal rise time is less than 60 ns, and the electronic equivalent capacitance noise is 19 eV/pF. The charge-sensitive preamplifier is connected to the Canberra PD450-17-100AM PIPS detector, and the standard α source 238Pu is measured in a vacuum environment. The energy resolution can reach 17keV@5499keV.