Author(s)

Taiki Hashizume, Masaya Yoshikawa, Masahiro Fukui

Department of Information Engineering, Meijo University, Nagoya, Japan.
Department of VLSI System Design, Ritsumeikan University, Kusatsu, Japan.

This paper discusses a high efficient parallel circuit simulator for iterative power grid optimization. The simulator is implemented by FPGA. We focus particularly on the following points: 1) Selection of the analysis method for power grid optimization, the proposed simulator introduces hardware-oriented fixed point arithmetic instead of floating point arithmetic. It accomplishes the high accuracy by selecting appropriate time step of the simulation; 2) The simulator achieves high speed simulation by developing dedicated hardware and adopting parallel processing. Experiments prove that the proposed simulator using 80 MHz FPGA and eight parallel processing achieves 35 times faster simulation than software processing with 2.8 GHz CPU while maintaining almost same accuracy in comparison with SPICE simulation.

Dedicated Hardware Accelerator; Power Grids Optimization; Parallel Circuit Simulator

T. Hashizume, M. Yoshikawa and M. Fukui, "A Parallel Circuit Simulator for Iterative Power Grids Optimization System," Circuits and Systems, Vol. 3 No. 2, 2012, pp. 153-160. doi: 10.4236/cs.2012.32020.