Dynamic and Leakage Power Estimation in Register Files Using Neural Networks ()
ABSTRACT
Efficient power consumption and energy dissipation in embedded devices and modern processors is becoming increasingly critical due to the limited energy supply available from the current battery technologies. It is vital for chip architects, circuit, and processor designers to evaluate the energy per access, the power consumption and power leakage in register files at an early stage of the design process in order to explore power/performance tradeoffs, and be able to adopt power efficient architectures and layouts. Power models and tools that would allow architects and designers the early prediction of power consumption in register files are vital to the design of energy-efficient systems. This paper presents a Radial Base Function (RBF) Artificial Neural Network (ANN) model for the prediction of energy/access and leakage power in standard cell register files designed using optimized Synopsys Design Ware components and an UMC 130 nm library. The ANN model predictions were compared against experimental results (obtained using detailed simulation) and a nonlinear regression-based model, and it is observed that the ANN model is very accurate and outperformed the nonlinear model in several statistical parameters. Using the trained ANN model, a parametric study was carried out to study the effect of the number of words in the file (D), the number of bit in one word (W) and the total number of Read and Write Ports (P) on the values of energy/access and the leakage power in standard cell register files.
Share and Cite:
A. Sagahyroon and J. Abdalla, "Dynamic and Leakage Power Estimation in Register Files Using Neural Networks,"
Circuits and Systems, Vol. 3 No. 2, 2012, pp. 119-125. doi:
10.4236/cs.2012.32016.