International Journal of Communications, Network and System Sciences

Vol.8 No.5(2015), Paper ID 56223, 8 pages

DOI:10.4236/ijcns.2015.85016

 

Ultra-Low Power Designing for CMOS Sequential Circuits

 

Patikineti Sreenivasulu, Srinivasa Rao, Vinaya Babu

 

ECE Department, JNTUK, Andhrapradesh, Kakinada, India
ECE Department, TRR College of Engineering, Hyderabad, India
CSE Department, JNTUH College of Engineering, Hyderabad, India

 

Copyright © 2015 Patikineti Sreenivasulu, Srinivasa Rao, Vinaya Babu et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

 

How to Cite this Article


Sreenivasulu, P. , Rao, S. and Babu, V. (2015) Ultra-Low Power Designing for CMOS Sequential Circuits. International Journal of Communications, Network and System Sciences, 8, 146-153. doi: 10.4236/ijcns.2015.85016.

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