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Mathematical Modeling and Performance Evaluation of 3D Ferroelectric Negative Capacitance FinFET
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A Pragmatic Quaternary FPGA Implemented with Floating Gate Memories
2021 IEEE 51st International Symposium on Multiple-Valued Logic (ISMVL),
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Multi-Level Design Influences on Robustness Evaluation of 7nm FinFET Technology
IEEE Transactions on Circuits and Systems I: Regular Papers,
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IEEE Journal of the Electron Devices Society,
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Analytical model of surface potential and threshold voltage in gate-drain overlap FinFET
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Analysis of 6 T SRAM cell in sub-45 nm CMOS and FinFET technologies
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Tunable work function in Junctionless Tunnel FETs for performance enhancement
Australian Journal of Electrical and Electronics Engineering,
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Journal of Materials Science: Materials in Electronics,
2017
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2017 20th International Conference of Computer and Information Technology (ICCIT),
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2015 Annual IEEE India Conference (INDICON),
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2015 International Conference on Emerging Research in Electronics, Computer Science and Technology (ICERECT),
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2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS),
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Performance evaluation of novel low leakage Double-gate FinFET device at sub-22nm with LaAlO3 high-k gate oxide and TiN metal gate using quantum modeling
2014 International Conference on Electronics and Communication Systems (ICECS),
2014
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Evaluating the impact of environment and physical variability on the ION current of 20nm FinFET devices
2014 24th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS),
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