New Analysis to Measure the Capacitance and Conductance of MOS Structure toward Small Size of VLSI Circuits

Wagah Farman Mohammad

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DOI: 10.4236/cs.2011.23022                

Abstract

In this research thin film layers have been prepared at alternate layers of resistive and dielectric deposited on appropriate substrates to form four – terminal R-Y-NR network. If the gate of the MOS structures deposited as a strip of resistor film like NiCr, the MOS structure can be analyzed as R-Y-NR network. A method of analysis has been proposed to measure the shunt capacitance and the shunt conductance of certain MOS samples. Mat lab program has been used to compute shunt capacitance and shunt conductance at different frequencies. The results computed by this method have been compared with the results obtained by LCR meter method and showed perfect coincident with each other.

Keywords

Thin Film R-Y-NR Network, MOS R-Y-NR Network, MOS-VLSI Circuits, MOS Capacitance

Conflicts of Interest

The authors declare no conflicts of interest.

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