FSM Based DFS Link for Network on Chip ()
ABSTRACT
As low power consumption
is the main design issue involved in a network on chip (NoC), researchers are
concentrating more on both algorithms and architectural approaches. The
conventional Dynamic Frequency
Scaling (DFS) and history based Frequency Scaling (HDFS) algorithms are
utilized to process the energy constrained data traffic. However, these
conventional algorithms achieve
higher energy efficiencies, and they result in performance degradation due to
the auxiliary latency between clock domains. In this paper, we present a
variable power optimization interface for NoC using
a Finite State Machine (FSM) approach to attain better performance improvement.
The parameters are estimated using 45 nm TSMCCMOS technology. In comparison
with DFS system, the evaluation
results show that FSM-DFS link achieves 81.55% dynamic power savings on the
links in the on-chip network, and
37.5% leakage power savings of the link. Also, this proposed work is evaluated for various performance
parameters and compared with conventional work. The simulation results are superior to
conventional work.
Share and Cite:
Sakthivel, E. , Malathi, V. , Arunraja, M. and Perumalvignesh, G. (2016) FSM Based DFS Link for Network on Chip.
Circuits and Systems,
7, 1734-1750. doi:
10.4236/cs.2016.78150.
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