Optimizing the Stage Resolution of a 10-Bit, 50 Ms/Sec Pipelined A/D Converter & Its Impact on Speed, Power, Area, and Linearity

Perala Prasad Rao, Kondepudi Lal Kishore

Department of Electronics and Communication Engineering, Jawaharlal Nehru Technological University, Hyderabad, India.

DOI: 10.4236/cs.2012.32022                

Abstract

At high speeds and high resolution, the Pipeline ADCs are becoming popular. The options of different stage resolutions in Pipelined ADCs and their effect on speed, power dissipation, linearity and area are discussed in this paper. The basic building blocks viz. Op-Amp Sample and Hold circuit, sub converter, D/A Converter and residue amplifier used in every stage is assumed to be identical. The sub converters are implemented using flash architectures. The paper implements a 10-bit 50 Mega Samples/Sec Pipelined A/D Converter using 1, 1.5, 2, 3, 4 and 5 bits/stage conversion techniques and discusses about its impact on speed, power, area, and linearity. The design implementation uses 0.18 μm CMOS technology and a 3.3 V power supply. The paper concludes stating that a resolution of 2 bits/stage is optimum for a Pipelined ADC and to reduce the design complexity, we may go up to 3 bits/stage.

Keywords

Switched Capacitor Sample and Hold Circuit; 1.5 Bits/Stage; Linearity; Power; Redundancy; Folded Cascode Op-Amp

Conflicts of Interest

The authors declare no conflicts of interest.

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