TITLE:
Incorporation of Reduced Full Adder and Half Adder into Wallace Multiplier and Improved Carry-Save Adder for Digital FIR Filter
AUTHORS:
S. Chinnapparaj, D. Somasundareswari
KEYWORDS:
Direct Form FIR Filter, Compact Full Adder and Half Adder, Improved Carry-Save Adder, Modified Wallace Multiplier, FPGA
JOURNAL NAME:
Circuits and Systems,
Vol.7 No.9,
July
22,
2016
ABSTRACT: Improvement of digital FIR
filter is vital in the field of Digital Signal Processing in order to reduce
the area, delay and power. Multiplication and Accumulation (MAC) unit of Finite
Impulse Response(FIR) filter has
been designed using efficient multiplier and adder circuits for optimized APT
(Area,Power and Timing) product. In this paper, the design of direct form FIR
filter with efficient MAC unit has been presented. Initially, full adder and
half adder structures are shrunk down by reducing number of gates. These
compact full adder and half adder structures are incorporated into Wallace
Multiplier and Improved Carry-Save Adder. The proposed 16-bit Carry-Save Adder
has been improved by splitting into four parallel phases. Consequently the
delay of enhanced Carry- Save Adder is reduced. Generation of carry output is
performed using number of OR gates in a sequential manner. All these enhanced
architectures are incorporated into the Digital FIR Filter to reduce the area,
delay and power utilization.