J. J. Yu and F. F. Dai, “A 3-Dimensional Vernier Ring Time-to-Digital Converter in 0.13?m CMOS”, IEEE Custom Integrated Circuit Conference (CICC), San Jose, 19-22 September 2010, pp. 1-4.

has been cited by the following article:

• TITLE: Single-Stage Vernier Time-to-Digital Converter with Sub-Gate Delay Time Resolution

  AUTHORS: Chin-Hsin Lin, Marek Syrzycki

  KEYWORDS: Vernier Time-to-Digital Converter, Dynamic-Logic Phase Frequency Detector

  JOURNAL NAME: Circuits and Systems, Vol.2 No.4, October 17, 2011

  ABSTRACT: This paperpresents a single-stage Vernier Time-to-Digital Converter (VTDC) that utilizes the dynamic-logic phase detector. The zero dead-zone characteristic of this phase detector allows for the single-stage VTDC to deliver sub-gate delay time resolution. The single-stage VTDC has been designed in 0.13μm CMOS technology. The simulation results demonstrate a linear input-output characteristic for input dynamic range from 0 to 1.6ns with a time resolution of 25ps.