Cu, X., Lui, W., Dong, W. and Lombardi, F. (2016) A Parallel Decimal Multiplier Using Hybrid Binary Coded Decimal (BCD) Codes. 2016 IEEE 23nd Symposium on Computer Arithmetic (ARITH), Santa Clara, CA, 10-13 July 2016, 150-155.
https://doi.org/10.1109/ARITH.2016.8

has been cited by the following article:

• TITLE: Efficient Realization of Vinculum Vedic BCD Multipliers for High Speed Applications

  AUTHORS: G. Sreelakshmi, Kaleem Fatima, B. K. Madhavi

  KEYWORDS: Signed Digit, Vedic Multiplier, Urdhav Triyagbhyam, Multi Operand Adder, VBCD Number System

  JOURNAL NAME: Circuits and Systems, Vol.9 No.6, June 29, 2018

  ABSTRACT: Decimal multipliers play an important role in our day to day life for commercial, financial and tax applications. Every processor multiplier acts as the basic building block which decides the performance of processor. Time and again research is going on to design high-performance, low-latency BCD multiplier architectures. This paper proposes a new approach to BCD multiplication using vinculum number system. The key feature of the proposed architecture uses entirely a new one digit ROM based BCD multiplier that uses vinculum numbers as operands. Using this one digit BCD multiplier, an N digit BCD multiplier is built by using the vedic vertical cross wire method (Urdhav Triyagbhyam). We have also used our proposed multi operand VBCD Adder (Vinculum BCD Adder) [my paper 26] to add the partial products. In this paper, we show that this approach is a promising alternative to conventional BCD multiplication or other decimal multiplication methods that use alternative decimal representations like 5211, 4221, Xs3 etc.