Barr, K.C., Pan, H., Zhang, M. and Asanovic, K. (2005) Accelerating Multiprocessor Simulation with a Memory Timestamp Record. Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, Ser. ISPASS’05, IEEE Computer Society, Washington DC, 66-77.
http://dx.doi.org/10.1109/ispass.2005.1430560

has been cited by the following article:

• TITLE: Multiple Levels of Abstraction in the Simulation of Microthreaded Many-Core Architectures

  AUTHORS: Irfan Uddin

  KEYWORDS: High-Level Simulations, Multiple Levels of Abstraction, Design Space Exploration, Many-Core Systems

  JOURNAL NAME: Open Journal of Modelling and Simulation, Vol.3 No.4, October 22, 2015

  ABSTRACT: Simulators are generally used during the design of computer architectures. Typically, different simulators with different levels of complexity, speed and accuracy are used. However, for early design space exploration, simulators with less complexity, high simulation speed and reasonable accuracy are desired. It is also required that these simulators have a short development time and that changes in the design require less effort in the implementation in order to perform experiments and see the effects of changes in the design. These simulators are termed high-level simulators in the context of computer architecture. In this paper, we present multiple levels of abstractions in a high-level simulation of a general-purpose many-core system, where the objective of every level is to improve the accuracy in simulation without significantly affecting the complexity and simulation speed.