TITLE:
An FPGA-Based Resource-Saving Hardware Accelerator for Deep Neural Network
AUTHORS:
Han Jia, Xuecheng Zou
KEYWORDS:
Deep Neural Network, Resource-Saving, Hardware Accelerator, Data Flow
JOURNAL NAME:
International Journal of Intelligence Science,
Vol.11 No.2,
March
30,
2021
ABSTRACT: With the development
of computer vision researches, due to the state-of-the-art performance on image
and video processing tasks, deep neural network (DNN) has been widely applied
in various applications (autonomous vehicles, weather forecasting,
counter-terrorism, surveillance, traffic management, etc.). However, to achieve
such performance, DNN models have become increasingly complicated and deeper,
and result in heavy computational stress. Thus, it is not sufficient for the
general central processing unit (CPU) processors to meet the real-time application
requirements. To deal with this bottleneck, research based on hardware acceleration
solution for DNN attracts great attention. Specifically, to meet various
real-life applications, DNN acceleration solutions mainly focus on issue of
hardware acceleration with intense memory and calculation resource. In this
paper, a novel resource-saving architecture based on Field Programmable Gate
Array (FPGA) is proposed. Due to the novel designed processing element (PE),
the proposed architecture achieves good
performance with the extremely limited calculating resource. The on-chip buffer
allocation helps enhance resource-saving performance on memory. Moreover, the
accelerator improves its performance by exploiting the sparsity property of the input feature map.
Compared to other state-of-the-art solutions based on FPGA, our
architecture achieves good performance, with quite limited resource
consumption, thus fully meet the requirement of real-time applications.