TITLE:
A Novel High-Performance Lekage-Tolerant, Wide Fan-In Domino Logic Circuit in Deep-Submicron Technology
AUTHORS:
Ajay Dadoria, Kavita Khare, T. K. Gupta, R. P. Singh
KEYWORDS:
High Speed Integrated Circuit, Dynamic Logic Circuit, Unity Noise Gain (UNG), Domino Logic Circuit, Noise Immunity
JOURNAL NAME:
Circuits and Systems,
Vol.6 No.4,
April
21,
2015
ABSTRACT: As technology shrinks in modern era the
demand on high speed, low power consumption and small chip area in
microprocessors is come into existence. In this paper we have presented a new
class of domino circuit design for low power consumption, faster circuit speed
and high performance. Due to wide fan-in domino logic, its logic gate suffer
from noise sensitivity, if we improve sensitivity, sub-threshold and gate oxide
leakage current dominate in evaluation network, which increases the power
consumption and reduces the performance of the circuit. The proposed circuit
improves the dynamic power consumption and reduces the delay which improves the
speed of the circuit. Simulation is performed in BISM4 Cadence environment at
65 nm process technology, with supply voltage 1 V at 100 MHz frequency and
bottleneck operating temperature of 27°C with CL = 1 fF. From the
result average power improvement by proposed circuit 1 & 2 for 8 input OR
gate is 10.1%, 15.28% SFLD, 48.56%, 51.49% CKD, 55.17%, 57.71% HSD and
improvement of delay is 1.10%, 12.76% SFLD, 19.13%, 28.63% CKD, 4.32%, 15.59%
HSD, 19.138%, 44.25% DFD respectively.