^{1}

^{*}

^{1}

^{1}

This paper describes a very low level dc current amplifier using switched capacitor (SC) circuit to miniaturize and improve its output response speed, instead of the conventionally used high-oh-mage resistor. A switched capacitor filter (SCF) and an offset controller are also used to decrease vibrations and offset voltage at the output of the amplifier. The simulation results show that the parasitic capacitances that are distributed to the input portion of the amplifier have some effect on offset voltage. From the experimental results, it is seen that the duty ratio of the clock cycle of SC circuit should be in the range from 0.05 to 0.70. It is suggested that the proposed very low level dc current amplifier using SC circuit is an effective way to obtain both a faster output response and its miniaturization.

When very small currents are measured by mass spectroscopes and radiation detectors, response speeds of the measuring instruments are limited by those of very low level dc current amplifiers [

In this paper, an amplifier with switched capacitor (SC) circuit and offset controller are proposed. The SC circuit is equivalent to a resistor and is suitable for miniaturization. We investigated how much effect parasitic capacitances in the SC circuit have on the amplifier’s output. Furthermore, effect of duty ratio of the clock cycle on the output of the amplifier was experimentally demonstrated.

From

and an electric charge

From Equation (1) and the relationship that

for

Circuit configurations of (a) very low level dc current amplifier; (b) SC negative feedback circuit and SCF. SC stands for switched capacitor

the electric charge

Since the current to be measured in the amplifier

while the equivalent SC resistance [

where

Thus, from Equations (4) to (6),

It is observed from Equation (6) that x is dependent on the ratio of capacitances of

The equivalent SC negative feedback circuit is illustrated in

Applying Millman’s theorem to

and

where

Equivalent circuits of (a) SC negative feedback circuit and (b) very low level dc current amplifier. (c) shows simplified input equivalent circuit of (b)

for

An enlarged input voltage waveform of the amplifier at the positive final steady-state,

Since electric charges of the SC circuit are conserved just before and after

The input voltage just before

From

From Equations (9) and (11), the input voltage just after

The resultant peak voltage

Substituting Equation (12) into Equation (13) gives the following equation:

Therefore, the peak output voltage of the amplifier during

Relationship between enlarged input voltage and clock waveform

It is found from Equation (15) that the theoretical output voltage of the very low level dc current amplifier using SC circuit can be obtained by sampling

To evaluate response speed of the very low level dc current amplifier, a square wave current

The amplification factor

Switch model used in PSpice simulation. Configurations of (a) nMOS, (b) pMOS FET models with parasitic capacitances, and (c) CMOS switch

. Parasitic capacitance values based on the assumption that nMOS and pMOS have the same parasitic capacitive components

Parasitic capacitance [pF] | ||||
---|---|---|---|---|

1.0 | 0.9 | 0.7 | 0.7 | 0.6 |

(MAX326, MAXIM Integrated Products, Inc.) having the maximum leakage current of 10 pA. Further, variable capacitors

First, based on the assumption that nMOS has exactly the same parasitic capacitances as pMOS has, transient analyses of the amplifier were done.

Simulation results with parasitic capacitances shown in Table 1. (a) Output waveform of very low level dc current amplifier using SC circuit; (b) its enlarged waveform at a positive final steady-state; and (c) output waveform of SCF. The rise time in (c) is 10.3 µs

SCF considerably reduces vibrations as well as unnecessary components, and that the input current

Secondly, we also performed computer simulations with an addition of 0.5 pF to each parasitic capacitance of nMOS or pMOS listed in

Experimental results are shown in

Finally, a relationship between the clock frequency

Output waveforms of the SCF with duty ratios of (a) d = 0.05; (b) d = 0.10; (c) d = 0.50; and (d) d = 0.70, respectively. Scale: H: 2.5 ms/div, V: 0.5 V/div

Relationship between the clock frequency and error rate of (x = 1/100)

. Parasitic capacitances in each switch that have effect on offset voltage of the amplifier

Parasitic capacitance [pF] | ||||
---|---|---|---|---|

It is found from the simulation results that the parasitic capacitive components that are distributed close to the input portion of the amplifier have effect on the offset voltage. The experimental results show that the duty ratio of the clock cycle has an effective range. The error rate of less than 3.0% in

We would like to thank anonymous referees for their valuable comments and suggestions.