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In order to improve the electrical and frequency characteristics of SiGe heterojunction bipolar transistors (HBTs), a novel structure of SOI SiGe heterojunction bipolar transistor is designed in this work. Compared with traditional SOI SiGe HBT, the proposed device structure has smaller window widths of emitter and collector areas. Under the act of additional uniaxial stress induced by Si
_{0.85}Ge
_{0.15}, all the collector region, base region and emitter region are strained, which is beneficial to improve the performance of SiGe HBTs. Employing the SILVACO
^{Ⓡ } TCAD tools, the numerical simulation results show that the maximum current gain
β
_{max}, the Earley voltage
V_{A} are achieved for 1062 and 186 V, respectively, the product of
β and
V_{A},
i.e.,
β ×
V_{A}, is 1.975 × 10
^{5} V and, the peak cutoff frequency
f
_{T} is 419 GHz when the Ge component in the base has configured to be a trapezoidal distribution. The proposed SOI SiGe HBT architecture has a 52.9% improvement in cutoff frequency
f
_{T} compared to the conventional SOI SiGe HBTs.

Recently, there has been increased interest in SiGe HBT technology for microwave RF circuits because of its high-frequency and compatibility with silicon technology [

In this paper, the proposed device improves the frequency characteristics by introducing stress, and uses SOI substrate structure with buried oxygen layer is used to reduce the self-heating effect brought by virtual substrate. First, the SOI technology and strain silicon technology are combined to introduce uniaxial stress into the SOI collector with N^{+} buried layer to form a new SOI SiGe HBT device structure. Then, the effects of Ge component on the current gain, Early voltage and cut-off frequency are briefly described. Finally, the structure has been proved to be able to achieve breakthroughs in the key frequency characteristics, i.e. f_{T} > 400 GHz.

In this paper, a two-dimensional device model is established by using SILVACO^{Ò} TCAD tools and the ATHENA module is then employed to simulate the process flow. The proposed device architecture is shown in

The widths of the emitter window and the collector window are 120 nm and 400 nm, respectively, which are following the size-reduction roadmap mentioned in ref. [_{1}_{−}_{y}Ge_{y} source and drain that commonly used in 90 nm, 65 nm and 45 nm CMOS process nodes, is now introduced in the collector region, where uniaxial compressive stress is consequently applied in the horizontal direction. Then, the Si_{1}_{−}_{x}Ge_{x} base is grown upon the strained collector. Due to the different lattice constants of Si and SiGe, the base region is subject to biaxial compressive stress [_{1}_{−}_{x}Ge_{x} base to build a double-layer “composite” emitter architecture [

The manufacture process simulation of the proposed SOI SiGe HBT mainly includes the following 6 steps: 1) Initialize (100) p-Si substrate; 2) Buried Oxide layer (BOX) is grown at 850˚C, then n^{+} buried layer and n^{−} collector are sequentially grown upon the BOX layer; 3) Two grooves are etched into the n^{−} collector

Region | Parameters | |||
---|---|---|---|---|

Material | Thickness (nm) | Doping (cm^{−3}) | Ge component | |

Strain silicon in Emitter | Si | 12 | 1 × 10^{18} | 0 |

Polysilicon in Emitter | Poly Si | 88 | 1 × 10^{20} | 0 |

Base | Si_{1}_{−}_{x}Ge_{x} | 20 | 1 × 10^{19} | 15 - 30 |

Collector | Si | 60 | 5 × 10^{17} | 0 |

Collector stress region | Si_{1}_{−}_{y}Ge_{y} | 60 | 0 | 15 |

N^{+} silicon | Si | 20 | 1 × 10^{20} | 0 |

Buried oxide | Oxide | 100 | 0 | 0 |

Silicon substrate | Si | 200 | 1 × 10^{15} | 0 |

layer where uniaxial stress generates or applies, and Si_{1}_{−}_{y}Ge_{y} is deposited in the etched grooves by selective epitaxy growth (SEG); 4) Electrode area of the collector is etched, and heavily-doped poly-silicon as the reach-through area of the collector is deposited; 5) P-type Si_{1}_{−}_{x}Ge_{x} base, heavily-doped P-type poly-silicon extrinsic base, and multi-layer emitter are successively deposited, and thin oxide films and poly-silicon are deposited by low-pressure chemical vapor deposition (LPCVD); 6) Aluminum (Al) film is finally produced on the whole surface by vacuum evaporation, any metal regions exterior to the electrodes are then removed by photolithography.

The design of the base region is mainly considered from two aspects, one is the boron doping concentration, the other is the distribution of Ge profile. This paper mainly studies the influence of different Ge profile according to the uniform boron doping concentration in the base region on device performance. The Ge profile in the base region can be classified into three types: box, triangle and trapezoid. Different Ge profile will affect the bandgap of the Si_{1}_{−}_{x}Ge_{x} base. The bandgap near to the emitter is reasonably configured to be larger than that near to the collector, so the built-in electric field is introduced to accelerate the transport of electrons [

Ge profile commonly used in the base of SiGe HBT, X_{0} is the boundary of the base near the emitter, X_{WB} is the boundary of the base near the collector, DE_{g}_{ }(X_{0}) is the band narrowing caused by Ge mole-fraction at X_{0}, and DE_{g}_{ }(X_{WB}) the band narrowing caused by Ge mole-fraction at X_{WB}. The relationship between the graded Ge fraction in the base and the current gain β is obtained by Equation (1) [

β SiGe β Si ∝ [ Δ E g , g r a d e / k T ] exp [ Δ E g ( X 0 ) / k T ] 1 − exp [ − Δ E g , g r a d e / k T ] (1)

Δ E g , g r a d e = Δ E g ( X W B ) − Δ E g ( X 0 ) (2)

The ratio of the current gain of SiGe HBT to that of Si BJT β_{max}/β_{Si} has an exponential relationship with DE_{g}_{ }(X_{0}). As shown as Equation (2), it is linear with the bandgap difference DE_{g}_{, }_{grade} caused by the graded Ge profile in the base. It can be seen that the Ge mole-fraction near the emitter has a significant effect on the current gain. The current gain with trapezoidal Ge distribution is larger than that with triangular Ge distribution when the content of Ge component in the base.

According to Equation (3) [_{g}_{, }_{grade}.

V A,SiGe V A,Si ∝ exp [ − Δ E g , g r a d e / k T ] − 1 Δ E g , g r a d e (3)

The relationship between the current gain and the optimal value of the Early voltage can be obtained [

β SiGe ⋅ V A,SiGe β Si ⋅ V A,Si ∝ exp [ Δ E g ( X 0 ) k T ] ⋅ exp [ Δ E g , g r a d e k T ] (4)

According to the above equations, the product of current gain and Early voltage of box Ge profile is smaller than that of Ge component gradient under the base Ge profile is constant.

In the device simulation, V_{CE} was 1.2 V and V_{BE} was varied from 0.1 to 1.2 V. The current gain is obtained and compared as shown in

above device structural model, the effects of three base Ge component distributions on current gain are obtained. It can be seen from the β-V_{BE} curve exhibited in _{max} of the box distribution of Ge component in the base is calculated as high as 2415, that of the trapezoid distribution β_{max} is 1062, and that of the triangle distribution β_{max} is 273. Therefore, the current gain of box type is the highest, which is following the above theoretical analysis.

Early voltage is one of the important parameters to characterize the electrical characteristics of devices. When the value of the Early voltage is larger, the width modulation effect in the base is smaller, and the concentration gradient of minority carrier in the base increases, hence the current gain β is naturally increased. The extraction of the value of the Early voltage is through the I_{C}-V_{CE} curve when I_{B} is set to be different constant and V_{CE} is close to zero, the tangent intersects the abscissa value, which corresponds to V_{A}. Therefore, the smoother the I_{C}-V_{CE} curve, the larger the V_{A}, and the better output characteristics of the device. When the base Ge component of SOI SiGe HBT is trapezoid-distributed, the output characteristic of the device is shown in _{C}-V_{CE} curves with I_{B} = 0.05 μA, 0.5 μA, 1 μA and 1.5 μA are selected. The curve is relatively smooth, and the calculated Early voltage V_{A} is about 186 V.

_{B} is a fixed value of 1.5 μA, which the influence of Ge component distribution on the output characteristic curve. It can be

seen from the figure that the curve of triangle distribution and trapezoid distribution is relatively smooth, while the curve of box distribution has the largest gradient and the Early voltage is the smallest. The results show that the Early voltage of trapezoid distribution is about 186 V, that of triangle distribution is about 224 V, and that of box distribution is 43 V.

From the simulation results, the maximum values of β × V_{A} of three Ge component distributions are summarized in

It can be concluded that the optimal values of current gain and Early voltage β × V_{A} are the highest when the base Ge component is trapezoidal.

Ge component distributions | |||
---|---|---|---|

box | trapezoid | triangle | |

β × V_{A} | 1.038 × 10^{5} V | 1.975 × 10^{5} V | 6.115 × 10^{4} V |

One of the key parameters to measure the electrical characteristics of devices is the cut-off frequency f_{T}, the change of Ge composition in the base mainly affects the transition time τ_{B} and the transition time τ_{E} in the emission region. Reducing these two-time constants can effectively improve the frequency characteristics of the device. According to Equation (5), when the base Ge component of SiGe HBT is slowly changing, the relationship between base transition time and emitter transition time and base Ge component respectively.

τ B,SiGe τ B,Si ∝ [ 1 − k T / Δ E g , g r a d e ] exp − Δ E g , g r a d e / k T Δ E g , g r a d e (5)

τ E,SiGe τ E,Si ∝ 1 − exp − Δ E g , g r a d e / k T Δ E g , g r a d e exp Δ E g ( X 0 ) / k T (6)

Among them, the DE_{g}_{, grade} is bandgap differences caused by gradient difference with insignificant Ge component variation. From Equation (5) that τ_{B}_{, SiGe} is smaller than τ_{B}_{, Si} due to the existence of bandgap difference. Therefore, the slow change of Ge component in the base region causes the gradual change of energy band to form a built-in electric field to accelerate the electron drift, which shortens the time of minority carrier crossing the base region. According to the formula, when the gradient of Ge component in the base increases, the cutoff frequency f_{T} will increase. From Equation (6), it can be obviously seen that the ratio of τ_{E}_{, SiGe}/τ_{E}_{, Si} is inversely proportional to the narrowing of the bandgap DE_{g}_{ }(X_{0}) caused by the Ge component on the side near the emission, and is linear with DE_{g}_{, grade}. Therefore, the key variable affecting the transit time τ_{e}_{, SiGe} of the emitter is DE_{g}_{ }(X_{0}). When the base Ge component is trapezoid distributed and the concentration of Ge component close to the emitter is not 0, the DE_{g}_{ }(X_{0}) and DE_{g}_{, grade} increase at the same time. It can effectively reduce the transit time of the emitter, thus increasing the cut-off frequency f_{T}.

The frequency characteristics of SOI SiGe HBT with different base Ge component distribution are obtained by the ATLAS simulation module as shown in _{T} and the maximum oscillation frequency f_{max} were extracted from s-parameter measurements extrapolating current gain h21 and unilateral gain U. The cut-off frequency f_{T} is the largest, up to 419 GHz, when V_{CE} = 4 V and the Ge component in the base is trapezoidal distribution; the cut-off frequency f_{T} is simulated as the value of 403 GHz when the Ge component is triangular distribution; the cut-off frequency f_{T} is 398 GHz when the

Ge component is box distribution. In conclusion, the best choice of Ge components in the base for the improvement of SOI SiGe HBT performance is an exactly trapezoidal distribution.

The simulation of the electrical characteristics of the small-size SOI SiGe HBT uses the ATLAS two-dimensional device simulation module. The main physical models used in the numerical simulation are concentration-dependent mobility model, parallel electric field dependence model, auger recombination model, Shockley-Read-Hall (SRH) recombination model, Band narrowing model, Stress model, energy balance transmission model and Fermi-Dirac statistical model. Newton iterative method and the Gummel iterative method are also used for numerical calculation.

The collector of SOI SiGe HBT also affects the frequency characteristics of the device, the smaller the delay time τ_{c} in the collector, the greater the cut-off frequency. This paper innovatively introduces the embedded Si_{1}_{−}_{y}Ge_{y} source drain strain technology in the collector (as shown in _{T} curves as a function of the collector for HBT device with stress and without stress are shown in _{T} of the traditional SOI SiGe HBT (without stress) is 197 GHz, while the improved SOI SiGe HBT (with

stress) is 419 GHz. The cut-off frequency f_{T} is increased by 52.9%. The improvement of collector optimization frequency is greater than that of base optimization frequency because the base is very thin and the transition time τ_{B} of the base is limited.

The simulation study of SiGe SOI HBT with strain into the collector. When the base Ge component distribution is a trapezoid, the influence of different base Ge component distribution on the SiGe HBT’s characteristics has been simulation and analysis. The maximum value of the current gain β_{max} is 1062, the value of the Early voltage V_{A} is 186 V, the product of the Early voltage and the current gain is 1.975 × 10^{5} V, and the maximum value of the cut-off frequency f_{T} is 419 GHz. The cut-off frequency is increased by 52.9% compared with the device structure without stress. The proposed novel SOI SiGe HBT device is compatible with the CMOS technology and has certain theoretical significance and reference value for the circuit design and process integration of commercial terahertz Si/SiGe BiCMOS in the future.

This work was financially supported by the National Natural Science Foundation of China (61704147, 61404019).

The authors declare no conflicts of interest regarding the publication of this paper.

Miao, N.D., Liu, P.P., Wen, J.H., Wei, J.X., Zhang, B.C., Wang, S.Q., Zeng, R.W., Wang, G.Y. and Zhou, C.Y. (2020) Design and Simulation of Improved SOI SiGe Hetero-Junction Bipolar Transistor Architecture with Strain Engineering. Journal of Applied Mathematics and Physics, 8, 218-228. https://doi.org/10.4236/jamp.2020.82017