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This paper presents the quasi-ballistic electron transport of a symmetric double-gate (DG) nano-MOSFET with 10 nm gate length and implementation of logical NOT transistor circuit using this nano-MOSFET. Theoretical calculation and simulation using NanoMOS have been done to obtain parameters such as ballistic efficiency, backscattering mean free path, backscattering coefficient, critical length, thermal velocity, capacitances, resistance and drain current. NanoMOS is an on-line device simulator. Theoretical and simulated drain current per micro of width is closely matched. Transistor loaded NOT gate is simulated using WinSpice. Theoretical and simulated value of rise time, fall time, propagation delay and maximum signal frequency of logical NOT transistor level circuit is closely matched. Quasi-ballistic transport has been investigated in this paper since modern MOSFET devices operate between the drift-diffusion and ballistic regimes. This paper aims to enable modern semiconductor device engineers to become familiar with both approaches.

In traditional semiconductor devices, carriers are frequently scattered from phonons, ionized impurities and surface roughness. In the traditional devices, the backscattering mean free path λ is much shorter than the device channel. So, drift-diffusion approach is used to describe the carrier transport. However, as devices downscale to nanometer regime, backscattering mean free path become comparable to transistor dimensions. When the backscattering mean free path becomes much larger than the transistor channel length, scattering can be totally ignored. In this situation, a nano-MOSFET behaves like a vacuum tube. In practical devices, scatterings are unavoidable in semiconductor devices. Therefore, modern devices operate in quasi-ballistic mode which is between drift-diffusion and ballistic regimes. Put in other words, drift-diffusion theory is no longer strictly valid as well as ballistic treatment. Hence, modern device engineer must familiar with both approaches. Then, the nano-MOSFET studied in this paper is applied in implementing logical NOT transistor level circuit [

Silicon (Si) MOSFETs currently operate between the ballistic and diffusive limits; the scattering model provides a conceptual model for transport in this quasi-ballistic regime. In this scattering model, the most important scatterings occur in the low-field region near the beginning of the channel at source side. Carrier scattering in the channel reduces the current and can be described by ballistic efficiency. Scattering model predicts that the drain current is close to the ballistic limit under high drain bias than under low drain bias, and the on-state current in strong inversion is limited by a small portion of the channel near the source, that is the top region of sub-band potential barrier.

The double-gate (DG) nano-MOSFET structure used in NanoMOS simulation is shown in

V_{GS } | 0.60 V |
---|---|

V_{DS} | 0.60 V |

V_{TO} | 0.20 V |

Source/drain doping concentration (N_{D}) | 1 × 10^{20} cm^{−3} |

Channel body acceptor impurity concentration (N_{A}) | 1 × 10^{16} cm^{−3} |

Channel width (W) | 125 nm |

Channel length (L) | 10 nm |

Source length/drain length (L_{SD}) | 7.5 nm |

Silicon channel thickness (T_{Si}) | 1.5 nm |

Top/bottom oxide insulator thickness (T_{OX}) | 1.5 nm |

Top/bottom insulator relative dielectric constant | 3.9 |

Channel body relative dielectric constant | 11.7 |

Top/bottom gate contact work function | 4.1888 eV |

The on-state current of the nano-MOSFET is controlled by a short low-field region close to the source end of the channel. The length l of this area is called critical length which is defined as the distance from the peak of the potential barrier to the point

where the potential reduces by

value of 1 for non-degenerate case and slightly greater than 1 for degenerate case. In this paper, take

The ballistic efficiency B is given by

where electron mobility at ballistic transport in Silicon is ^{2}/Vs. The thermal velocity is given by

where

Since lower bound for

In studying the theoretical part of this paper, the following Fermi-Dirac integrals are used:

where

After considering the ballistic efficiency B,

is the gate oxide capacitance per unit area

The on-line current-voltage (I-V) simulation result of NanoMOS is compared with theoretical calculation using Equation (11).

In order to calculate resistance R_{Load} of nano-MOSFET at quasi-ballistic limit, uses

Since digital logic gates operate at linear portion of I-V curve. This R_{Load} is used in analyzing rise time of transistor loaded NOT gate circuit. On the other hand, the following expression is used to obtain on-state channel resistance R_{channel at on-state} which is used in fall time analysis.

^{2}/Vs.

Transistor loaded NOT gate as shown in

Since the nano-MOSFET operates at quasi-ballistic condition:

From

From [_{G}, C_{S} and C_{D} can be calculated.

Total Capacitance of NOT gate = Gate Capacitance + Source Capacitance + Drain Capacitance + Area Capacitance + Sidewall Capacitance.

Rise time constant

Rise time

Fall time constant

Fall time

Propagation delay

Maximum signal frequency

_{DS} lowers the sub-band potential at the drain side by 0.60 eV [

From Equation (3), the backscattering mean free path is

From Equation (5), the critical length is

From Equation (1), the backscattering coefficient is

From Equation (2), the ballistic efficiency is

In order to analyze the NanoMOS simulation result of _{DS} = 0.60 V.

Then, by using Equation (10),

After considering the ballistic efficiency B and using Equation (11),

Simulated result with NanoMOS, as in

87.3% closely matched. In

At region above threshold, the Fermi-Dirac integrals in Equation (11) can be simplified to exponential terms as in equation below.

Sub-band potential at drain side is lower by

Then Equation (19) becomes

After analysis, Equation (19) and Equation (20) both has the same value.

To implement transistor level NOT gate circuit as in _{DS} = 0.00 V until 0.20 V. Use Equation (11) to calculate the drain current at this linear region and then apply Equation (17) to calculate R_{Load} at quasi-ballistic limit. From Equation (11),

In order to calculate the resistance of nano-MOSFET at quasi-ballistic limit, use Equation (17) since digital logic gates operate at linear portion of I-V curve. Using V_{th} =

0.20 V, _{Load} = 748.8

Ω. The resistance value is used in analyzing theoretical value of rise time in NOT gate circuit. On the other hand Equation (18) is used to obtain the resistance needed in analyzing theoretical value of fall time in NOT gate circuit. Finally, the NOT gate circuit in

Low output voltage V_{OL} of NOT transistor level circuit in

From WinSpice simulation timing diagram

By comparing Equation (21) and Equation (22),

From theoretical modeling and also WinSpice simulation, V_{OH} = 0.4 V. Nano- MOSFET at the bottom is at off state and thereby at high impedance state. Threshold voltage lost 0.20 V occurs at top side nano-MOSFET load which acts as pass transistor.

Modern MOSFET semiconductor devices operate in quasi-ballistic transport. Quasi- ballistic transport is the carrier transport between drift-diffusion and ballistic regimes.

Parameters | ||
---|---|---|

Gate capacitance (F) | 5.7551E−17 | |

Area capacitance (F) | 1.6125E−19 | |

Sidewall capacitance (F) | 6.0720E−17 | |

Total drain capacitance (F) | 4.6041E−18 | |

Total source capacitance (F) | 1.0469E−17 | |

NOT gate total capacitance (F) | 1.3400E−16 | |

Load resistance (ohm) | 748.8 | |

On-state channel resistance (ohm) | 36.2 | |

Theoretical value | WinSpice simulated value | |

Rise time constant | 9.9969E−14 | 1.2645E−13 |

Rise time (s) | 1.3416E−12 | 1.6969E−12 |

Fall time constant | 4.8329E−15 | 1.1000E−13 |

Fall time (s) | 1.0632E−14 | 2.4200E−13 |

Propagation delay (s) | 3.6322E−14 | 8.2756E−14 |

Maximum frequency (Hz) | 7.3953E+11 | 5.1600E+11 |

Theoretical calculations and simulation results about this transport have been done in this paper and this paper shows that theoretical calculation values and simulation results are closely matched. Logic NOT circuit level has been implemented using nano- MOSFET and correct logical operation has been achieved.

Ooi, C.Y. and Lim, S.K. (2016) Study of Timing Characteristics of NOT Gate Transistor Level Circuit Implemented Using Nano-MOSFET by Analyzing Sub-Band Potential Energy Profile and Current-Voltage Characteristic of Quasi-Ballistic Transport. World Journal of Nano Science and Engineering, 6, 177-188. http://dx.doi.org/10.4236/wjnse.2016.64016