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Threshold voltage (V
_{TH}
) is the most evocative aspect of MOSFET operation. It is the crucial device constraint to model on-off transition characteristics. Precise V
_{TH}
value of the device is extracted and evaluated by several estimation techniques. However
,
these assessed values of V_{TH} diverge from the exact values due to various short channel effects (SCEs) and non-idealities present in the device. Numerous prevalent V_{TH} extraction methods are discussed. All the results are verified by extensive 2-D TCAD simulation and confirmed through analytical results
at
10-nm technology node. Aim of this research paper is to explore and present a comparative study of largely applied threshold extraction methods for bulk driven nano-MOSFETs especially
at
10-nm technology node along with various sub 45-nm technology nodes. Application of the threshold extraction methods to implement noise analysis is briefly presented to infer the most appropriate extraction method at nanometer technology nodes.

Incessant abridging of IC technology, together with precision of V_{TH} control techniques and reduction in SCE, is asserting the V_{TH} to very low values. For proper operation of MOSFET, we need to evaluate exact threshold voltage (V_{TH}). Perfectly appraised V_{TH} is required to provide proper gate control over device channel conduction (see _{TH} is essential to illustrate the exact device behaviour [_{TH} values. V_{TH} is frequently used for accessing and predicting device performance. It is also commonly used to check the inconsistency due to manufacturing process technological parameter fluctuations. Other applications of V_{TH} can be listed as to evaluate reliability factors such as radiation damage, hot carrier, stress, temperature instability, ageing degradation etc.

The threshold voltage parameter is largely extracted directly from the transfer characteristics of the device. There is no critical point in the I_{D}-V_{GS} curve that can be recognized as threshold point due to sub-threshold leakage current. This creates vagueness in V_{TH} estimation. The weak inversion region shows exponential deviations while strong inversion shows linear/quadratic deviations. However, the V_{TH} is identified amid weak and strong inversion transition region [_{TH} also depends on several device parameters (Gate width, Gate Overlap, Gate length, biased bulk, temperature etc.) and process technology limitations (Cox, tox, doping concentration (NA) etc.) [_{TH} estimation more challenging.

In consideration to the above, this paper presents the study and analysis of numerous V_{TH} extraction methods at various sub 45-nm technology node. The outcomes of the analysis are implemented on a simple resistive load inverter for computing noise margins to infer the performance of various threshold voltage extraction methods at sub 45-nm technology node.

Rest of the paper is organized as follows. Section 2 categorizes several threshold voltage extraction methods on the basis of their assessment methodology. Section 3 to Section 8 discuss and evaluate the various mentioned threshold voltage extraction methods at 10-nm technology node and other sub 45-nm technology nodes. Further, Section 9 presents the tabulated compiled simulation results, comparison and discussion for various sub 45-nm technology nodes. Application of the threshold extraction methods to implement noise analysis is briefly presented in Section 10. Finally, concluding remarks

are conferred in Section 11.

Ideally, V_{TH} of a device is the critical gate voltage below which the drain to source current (I_{D}) is zero, But practically, sub-threshold leakage current exists for V_{GS} below V_{TH}. As the drain current doesn’t drop abruptly to zero and hence, it becomes challenging to precisely determine the critical point at which switching of I_{D} takes place. Due to this reason, several procedures presented in literature use diverse descriptions to extract the V_{TH} of the MOSFET but still has a scope for improvement to correctly evaluate V_{TH} [_{TH} extraction techniques and examines these for simplified square-sized NMOS device at 10-nm technology node. For precise evaluation of the methods, the process is reiterated in similar conditions on other sub 45-nm technology nodes [

For simplicity, the threshold extraction methods have been categorized into six main groups on the basis of their assessment methodology as:

1) I_{D} based extraction methods;

2) Derivative of I_{D} based extraction methods;

3) Integral of I_{D} based extraction methods;

4) Self-extraction methods;

5) Deviation based extraction methods;

6) Hybrid extraction methods.

It is considered that the threshold voltage changes with the change in the operating region of the MOSFET specifically in linear/ triode region and saturation region. Distinctive efforts are made to accurately calculate the V_{TH} in both the operating regions [_{TH} are evaluated as V_{LIN} and V_{TSAT} for all the discoursed methods on our test device.

These methods use the drain current (I_{D}) directly in the extraction method of threshold voltage. Some common methods listed underneath are briefly discussed below.

This method determines V_{TH} as the gate voltage for an arbitrary critical drain current (I_{DCRITICAL}) value [_{TH} using this method, I_{D} versus V_{GS} graph is plotted on a semi-logarithmic scale for two extreme values of V_{DS} i.e. high biased and low biased. For our test device, we considered V_{DS} = 0.9 V and V_{DS} = 0.1 V respectively. The I_{DCRITICAL} is technology reliant, generally considered as (0.1 μA) × (W/L), where W and L are the gate width and gate length.

I_{DCRITICAL} referred in Equation (1) is designated such that V_{TH} is on the transition point of linear-sub-threshold region of the device [

Implementation of CCM on Test Device

The technique was implemented on our test device square-sized NMOS with 10-nm technology node and was repeated in similar conditions on other sub 45-nm technology nodes. _{TLIN} and V_{TSAT}) using CCM on our test device.

The outcome of the results was as follows:

Diffusion current governs the total current in sub-threshold region whereas drift current dominates in strong inversion region. This DDEM process states that by applying low drain voltage (V_{DS} ≈ 0.1 V), the threshold voltage is the distinctive gate voltage at which the condition I_{DRIFT} = I_{DIFFUSION} holds true [

where I_{Drift} and I_{Diffusion} represent the drift current and diffusion current respectively.

Implementation of DDEM on Test Device

The technique was implemented on the test device.

The outcome of the result was as follows:

The DDEM process has the restriction of low biased V_{DS} = 0.1 V. Since the device is always made to operate in linear region, hence the saturation region threshold voltage V_{TSAT} could not be calculated. _{DRIFT} and I_{DIFFUSION} with the variation in V_{GS} to extract the threshold voltage.

These methods use the derivative or the higher order derivate of the drain current value in the extraction method of threshold voltage. Fundamental V_{TH} extraction methods using this respective technique are briefly discussed below.

In this LEM technique, we determine the V_{TH} of the transistor using transconductance (g_{m}) and I_{DS}-V_{GS} curve. The g_{m} is defined as the derivative (slope) of I_{D}-V_{GS} relationship. The extreme g_{m} obtained on the I_{D}-V_{GS} characteristic curve is used to extrapolate the gate voltage (V_{GS}) as shown in _{GS} is extracted V_{TH} for the given conditions. The I_{D} for linear region is associated with V_{GS} as:

This LEM process provides clear steps for V_{TH} assessment but it is partial to linear region of operation i.e. for low values of V_{DS}. Maximum g_{m} point is not obtainable for higher values of V_{DS}. Furthermore, the DIBL effect also comes into picture for higher V_{DS} and diminishes effective V_{TH} values. Apart from these issues, this method also lacks to determine a constant V_{TH} as dissimilar methods used for attaining maximum g_{m} values. g_{m} also depends on SCEs such as velocity saturation, overlap variations, extrinsic resistance, channel length modulation and so on. This reliance of g_{m} and critical point of maximum g_{m} is tough to accurately model. Henceforth, this produces loopholes in this process to precisely evaluate the V_{TH}.

Implementation of LEM on Test Device

The technique was implemented on the test device.

The outcome of the result was as follows:

As described above, the Maximum g_{m} is not obtainable for higher values of V_{DS}. Hence special efforts were made to calculate V_{TSAT} using this method. _{m} variation with the variation in V_{GS} at constant V_{DS} = 0.1 V.

Technique named Quadratic Extrapolation Method (QEM) is also called as “Linear Extrapolation in Saturation Region”. It is used to calculate threshold voltage using LEM in saturation region (V_{TSAT}). As mentioned in LEM, the I_{D} for linear region is proportional to (V_{GS} − V_{TH}). Similarly, I_{D} in saturation region is proportional to (V_{GS} − V_{TH})^{2} as shown in Equation (4):

Hence V_{TSAT} can be extracted by extrapolating the curve _{GS} at the inflexion point of the curve as shown in

Implementation of QEM on Test Device

The technique was implemented on the test device.

The outcome of the result was as follows:

The second-derivative method (SDM), formerly entitled as transconductance change method [_{TH} as the V_{GS} value at which the derivative of the transconductance (i.e.,

_{D} = 0 for V_{G} < V_{T}, and I_{D} is directly proportional to V_{G} for V_{G} > V_{T}. With these suppositions, dI_{D}/dV_{G} becomes a step function, which is zero for V_{G} < V_{T} and is a positive constant for V_{G} > V_{T}. Therefore,

_{G} = V_{T}. Such a simple assumption is apparently not true in a real device, and thus _{T}. However, it will exhibit a maximum value at V_{GS} = V_{TH}. _{TLIN} extraction at constant V_{DS} = 0.1 V.

The execution of this SDM process in the linear region is extremely sensitive to

measurement error and noise, as the second derivative amounts to applying a high-pass filter to the measurement [

Implementation of SDM on Test Device

The technique was implemented on the test device. The process was widely affected by noise. Special possessions of filtration and smoothening of curve were considered to extract the correct output as shown in

The outcome of the result was as follows:

In this TDM process, it has been proposed that the V_{TH} can be extracted from the value

of V_{GS} at which the third derivative of the current I_{D} (i.e.,^{3}I_{D}/dV_{GS}^{3}.

_{TH} value would still be irreconcilable with that extracted by the SD method.

Implementation of TDM on Test Device

The technique was implemented on the test device. The method was vastly affected by the investigational noise. Hence it was challenging to extract the threshold values. Special properties of smoothening and filtration of the curve were considered to extract the correct output. Even after high considerations, it was observed that V_{TLIN} value was lower than V_{TSAT} value which is commonly unusual.

The outcome of the result was as follows:

The CsrTR method formerly called as Ghibaudo Method (GM) was developed to dodge the extracted V_{TH} value dependence on mobility degradation and parasitic series resistance [

The GM technique, also occasionally called as ‘‘the modified Y function method’’, has been freshly enhanced for application to contemporary devices using a more universal mobility degradation model.

The V_{TH} is extracted from the intercept of the GM versus V_{GS} linear fit. _{GS} axis intercept. It does not evidently show the supposedly expected linear behavior. Therefore, the linear extrapolation shown in

Implementation of Ghibaudo Method (GM) on Test Device

The technique was implemented on the test device. Non-linearity in the curve caused difficulties in extrapolation process to estimate the required values.

The outcome of the result was as follows:

This method is based on calculating TCR as the ratio of transconductance to the drain current as described in Equation (6) [

It states that the threshold voltage can be determined as the value of V_{GS} where TCR presents its maximum negative slope i.e. V_{GS} corresponding to the minimum value of curve dTCR/dV_{GS}. However, considering TCR by itself significantly increases random tentative noise, specifically in weak inversion.

Implementation of TCR Method on Test Device

The technique was implemented on the test device. The method was highly affected by the investigational noise as seen in _{TLIN}

and V_{TSAT} respectively. Hence it was challenging to extract the threshold values. Filtration and smoothening of the curve like properties were applied to extract the correct output. Even after high considerations, it was observed that V_{TLIN} value was lower than V_{TSAT} value which is generally unusual.

The outcome of the result was as follows:

These methods use the integral of the drain current value in the extraction method of threshold voltage. Prevalent V_{TH} extraction methods using this technique are briefly discussed below [

This TM technique was stimulated by the properties of the integral difference function D(V,I), which had been formerly defined for two-terminal device as [

As shown in Equation (7), this function presents the advantageous features of eradicating the effect of any linear element (resistance) coupled in series with the device. To extract V_{TH}, the drain current is constantly measured from below the expected value of V_{TH} versus V_{GS} with a small constant drain voltage (V_{DS} ≈ 100 mV). Subsequently, the succeeding function TM is numerically calculated from the measured data:

where V_{G0} represents the lower limit of integration analogous to a gate voltage well below threshold in Equation (8). Usually chosen V_{G0} = 0. The logic of the method is based on the ideal case of a MOSFET, piecewise modelled as: I_{D} = I_{LEAKAGE} for V_{GS} < V_{TH} and I_{D} is proportional to V_{GS} for V_{GS} > V_{TH}. Using the previous streamlining supposition, we observe that:

1) Function TM presents a discontinuity at V_{TH};

2) TM = −V_{GS} for V_{GS} < V_{TH}; and

3) TM = +V_{TH} for V_{GS} > V_{TH}.

Since for a real device such simplifying conventions are apparently not precisely true, function TM will present an extreme value due to the mobility degradation and its value will be close to V_{TH}.

A plot of TM versus V_{GS} or ln(I_{D}) should result in a straight line below threshold, where the current is dominated by diffusion and is principally exponential. As soon as V_{GS} = V_{TH}, the function TM should vitiate due to mobility degradation. The specified logic accords with the test device as shown in _{TH} value of the device. The shape of the curve is swayed by the parasitic resistance and mobility degradation effects, but not significantly its maxima, lest those effects are exceedingly prominent. Hence, the parasitic series resistance consequence is not totally eradicated since a MOSFET is not a two-terminal device with node current as I_{D} and node voltage as V_{GS}. _{GS} to extract V_{TSAT} for V_{DS} = 0.9 V.

Implementation of TM Process on Test Device

The technique was implemented on the test device. Smooth curves were obtained. Hence it was easy to extract the threshold values. The V_{TLIN} value and V_{TSAT} value can also be extracted through the TM versus I_{D} curve using the same procedure. On implementation of the mentioned logic, we got the same agreeing values of the threshold voltages.

The outcome of the result was as follows:

The NMID method was initially developed by He and co-workers in 2002 and it was also stimulated by the integral difference function NMID [_{D}V_{GS} as shown in Equation (9):

Consequently, a plot of NMID versus V_{GS} will characterize a maxima at V_{GS} = V_{TH}. _{GS} value.

Implementation of NMID Process on Test Device

The technique was implemented on the test device. Smooth curves were obtained. Flat curves of NMID to evaluate NMID max was challenging to extract the analogous threshold values. _{GS} to extract V_{TSAT} for V_{DS} = 0.9 V.

The outcome of the result was as follows:

The NRH method can also be labelled as “Improved NMID Method”. Eliminating the ‘‘1’’ term and the factor ‘‘2’’ from NMID Equation (11), and considering that I_{D} ≠ 0 at V_{GS} = 0, yields a normalized version of the NRH function originally proposed in 2001 for extracting the threshold voltage of amorphous thin film MOSFETs, and later revised in 2010 to evaluate the sub-threshold slope of MOSFETs. Mathematically, the H function is represented as follows [

where I_{D0} is the drain current at V_{GS} = 0. Limit of the integral can be considered as 0 to V_{GS} in Equation (10). We propose that instead of using H(V_{GS}) function, its reciprocal NRH(V_{GS}) should be used to produce narrow maxima or minima:

A factor of 2 is added to the denominator in Equation (11) to allow a simple graphical explanation of its meaning. The numerator divided by 2 is the area of a triangle with a width of V_{GS} and a height of I_{D} − I_{D0}. Then, NRH is the ratio of this triangle’s area divided by the area under the plot (the integral). _{TLIN} and V_{TSAT} respectively.

Implementation of NRH Method on Test Device

The technique was implemented on the test device. Smooth curves were obtained. Flat curves of NRH to evaluate NRH max was challenging to extract the analogous threshold values.

The outcome of the result was as follows:

In view of TCR, the differential value of I_{D} by itself expressively increases experimental noise, specifically in weak inversion, an analogous function for low gate bias. The plot of dRH/dV_{GS} versus V_{GS} exemplifies the above statement as it can be clearly seen in

where RH is the reciprocal of function H predefined in NRH method; I_{D0} is the drain current flow at V_{GS} = 0. Limits of the integral can be considered as 0 to V_{GS}. It is anticipated that the RH function could also be used to extract the threshold voltage. The V_{TH} can be extracted from the maximum negative gradient of the function RH i.e. V_{GS} = V_{TH} analogous to the minimum value of curve dRH/dV_{GS}.

Implementation of RH Method on Test Device

The technique was implemented on the test device. The method was highly affected by the investigational noise. Hence it was challenging to extract the threshold values. As seen in

The outcome of the result was as follows:

These methods use the self-extracting techniques and circuits to extract the value of threshold voltage. Couple of methods under this category are briefly discussed below.

A substantially enhanced HSPICE feature that extracts MOSFET threshold voltage (V_{TH}) based on the constant-current definition universally adopted by fabrication labs to measure, specify, and monitor V_{TH}. Introduced in the 2009.09 release, HSPICE simulations compute constant-current V_{TH} the exact same way V_{TH} is measured in the fab [

For extracting V_{TH}, the “.OPTION IVTH” command is available. This .OPTION IVTH feature is supported for Levels 54 (BSIM4), 69 (PSP100), and 70 (BSIMSOI4) MOSFET models along with latest PTM nano-MOSFET models. It shows acceptable results. This command extracts V_{TH} using CCM and eliminates the use of I_{DCRITICAL}. LX142 model accessible in HSPICE, presents the output results as V_{TH}. Therefore, for short channel devices this process appears effectual in extracting V_{TH} and also shows compatibility with the existing transistor models.

The HSPICE Command “.OPTION IVTH” was implemented on the test device. LX142 model accessible in HSPICE, presents the output results as V_{TH}.

The outcome of the result was as follows:

This proposed ATEC method implements the most popular industrial extraction algorithm (LEM) of biasing a saturated MOSFET to the linear portion of its _{GS} characteristics and extrapolating the tangential line to V_{GS} axis [_{TH} using the proposed logic. Conceptual Schematic of ATEC is shown in

Few other similar ATEC designs with different implementation logics are also proposed to extract the V_{TH}.

Implementation of ATEC Method on Test Device

The technique was implemented on the test device. The bulk driven 10 nm nano- NMOS model was used to simulate the circuit. The test device is made to work in linear region. Hence the outcome will be the threshold voltage in linear region (V_{TLIN}). The transient analysis of the circuit gave the following results as shown in

Under this grouping, the V_{TH} is extracted by determining either the deviation of the value or the difference between the measured values. Couple of methods using this logic are listed in this category and are briefly discussed below [

Match-Point method was proposed in 1990 by B. El-Kareh and co-workers. This scheme subjectively evaluates V_{TH} at the value of V_{GS} at which the exponential subthreshold current semi-log extrapolation diverges by 5% from the measured I_{D}.

This MP method exaggerates the weak inversion region neglecting strong inversion.

and saturation region our test device producing an apparent V_{TH} value V_{TLIN} of 0.51 V and V_{TSAT} of 0.52 V respectively. Of course, diverse values of V_{TH} could be arbitrarily achieved by defining the deviation of the extrapolation at threshold at other values different from 5%. The shape of the semi-log curve may be swayed by the presence of parasitic resistance and other SCEs. This method is seldom used as it is more laborious and time consuming.

Implementation of MP Method on Test Device

The technique was implemented on the test device. Generally Match Point method is used to calculate threshold Values by plotting I_{D} versus V_{GS} curve with low biased drain terminal. Hence outcome is V_{TLIN}. The results are extracted by using the semilog plot. We propose to calculate V_{TSAT} by plotting _{GS} and applying the same 5% deviation logic of Match point method. It was observed that V_{TLIN} value was lower than V_{TSAT} value which is generally unusual.

The outcome of the result was as follows:

In this VVD method, a new interpretation of the threshold voltage is presented as [

The method is implemented by performing the transient analysis on the testing device. In other words, it states that V_{TH} can be extracted by the voltage difference between the constant V_{G} and V_{S} at the normalized current in the I_{D}-V_{S} curves. As seen in

Implementation of VVD Method on Test Device

The technique was implemented on the test device.

results of the VVD circuit. The circuit was compiled and simulated using SPICE. The circuit was analysed using predictive technology model (PTM) at 10-nm, 16-nm, 22-nm, 32-nm, and 45-nm technology node. The input gate voltage was set as 0.9 V. The Vdd was given as constant DC supply of 0.9 V. The multiple values of Load Capacitances (Cload) were used for the testing purpose, however, the V_{TH} extraction results had negligible effect of the variations in the value. Transient analyses were performed on the compiled circuit to extract the threshold voltage value.

The outcome of the result was as follows:

The transient results gave the V_{out} value marginally equal to V_{in}, slightly a bit millivolts lower than V_{in}. Hence, as per the above mentioned logic of the referred extraction method, the calculated V_{TH} is a very small value in millivolts which was not in accord with other extraction method outcomes. The extracted threshold voltage value also seems to be unrealistic. Hence we can accomplish that the VVD extraction method is considerably ineffective at nano-meter technology node.

Under this category, the HEM process uses multiple recognized schemes to extract V_{TH} and combines the advantage of each. One of the hybrid extraction methods is explained below [

This Hybrid extraction method overwhelms the constraints of above mentioned extraction techniques and compute V_{TH} for all values of V_{DS}. It syndicates both methods namely CCM and LEM mentioned beforehand to appropriately extract the V_{TH}. Additionally, this method is also unaffected by the arbitrary value of I_{DCITICAL}. For valuation of V_{TH} using this method first the value of V_{TH} for low biased V_{DS} is attained using LEM (see _{DCRITICAL} is determined using CCM as mentioned above. Further, for higher value of V_{DS}, V_{TH} is defined as the gate voltage at I_{D} for pre-calcu- lated I_{DCRITICAL} value. However, the extracted value of V_{TH} is not constant as the dependence of g_{m} on other process parameters is not modelled accurately.

Implementation of Hybrid Extraction Method on Test Device

The HEM technique was implemented on the test device. V_{TLIN} was calculated using LEM for I_{D} versus V_{GS} graph with low biased V_{DS}, and correspondingly the I_{DCRITICAL} was also evaluated. Furthermore, I_{D} versus V_{GS} graph is plotted with high biased V_{DS}. Implementing the CCM technique on the plot by using the pre-calculated I_{DCRITICAL}, we are able to calculate V_{TSAT}. Hence we are able to extract V_{TLIN} and V_{TSAT} using Hybrid extraction method as seen in

The outcome of the result was as follows:

All the predefined threshold voltage extraction methods were investigated and implemented at 10-nm Technology node and other sub 45-nm technology node. All the results are verified by extensive 2-D TCAD simulation and confirmed analytically. Various predictive technology models developed by the Nanoscale Integrations and Modelling (NIMO) Group at Arizona State University (ASU) were used to illustrate the characteristics of nano-MOSFETs. The models possess the competency to support short

channel effects, the gate leakage effects and various other second order effects to predict the realistic output. _{TH} was analysed using predictive technology model (PTM) for bulk driven nano-mosfet at 10-nm, 16-nm, 22-nm, 32-nm and 45-nm technology node.

The results are tabulated in

Noise analysis of the Resistive load Inverter were performed using various V_{TH} extraction method values. Resistive load inverter is one of the most fundamental circuits of MOS family. It characterizes the basic operation of all static gates. With Load resistor (R_{L}) in series with driver NMOS transistor, it has one input connected to the gate of NMOS and one output port connected to the drain terminal of the NMOS as shown in _{TH} (inverter) is the value where output voltage is equal to input voltage.

Noise margin is the limit of noise that a circuit can endure without compromising the operation of circuit. It assures that logic “1” with finite noise added to it, is still recognized as logic “1” and not logic “0” and vice versa. It is principally the difference between

METHOD | 10-nm TN | 16-nm TN | 22-nm TN | 32-nm TN | 45-nm TN | |||||
---|---|---|---|---|---|---|---|---|---|---|

V_{TLIN} | V_{TSAT} | V_{TLIN} | V_{TSAT} | V_{TLIN} | V_{TSAT} | V_{TLIN} | V_{TSAT} | V_{TLIN} | V_{TSAT} | |

CCM | 0.355 | 0.104 | 0.463 | 0.369 | 0.479 | 0.425 | 0.440 | 0.396 | 0.433 | 0.403 |

DDEM | 0.44 | N.A | 0.45 | N.A | 0.47 | N.A | 0.46 | N.A | 0.45 | N.A |

LEM | 0.683 | N.A | 0.719 | N.A | 0.706 | N.A | 0.653 | N.A | 0.634 | N.A |

QEM | N.A | 0.381 | N.A | 0.535 | N.A | 0.564 | N.A | 0.526 | N.A | 0.522 |

SDM | 0.675 | 0.437 | 0.7 | 0.6 | 0.675 | 0.6 | 0.649 | 0.552 | 0.626 | 0.578 |

TDM | 0.559 | 0.363 | 0.65 | 0.504 | 0.65 | 0.525 | 0.595 | 0.5 | 0.578 | 0.5 |

GM | 0.59 | 0.51 | 0.645 | 0.575 | 0.645 | 0.56 | 0.6 | 0.525 | 0.6 | 0.5 |

TCRM | 0.65 | 0.5 | 0.675 | 0.6 | 0.675 | 0.625 | 0.625 | 0.6 | 0.6 | 0.575 |

TM | 0.645 | 0.5 | 0.65 | 0.575 | 0.675 | 0.575 | 0.625 | 0.525 | 0.6 | 0.513 |

NMID | 0.625 | 0.65 | 0.625 | 0.65 | 0.625 | 0.65 | 0.6 | 0.625 | 0.575 | 0.6 |

NRHM | 0.625 | 0.65 | 0.65 | 0.675 | 0.65 | 0.675 | 0.6 | 0.625 | 0.575 | 0.6 |

RHM | 0.675 | 0.675 | 0.7 | 0.725 | 0.725 | 0.725 | 0.675 | 0.7 | 0.65 | 0.675 |

SPICE | 0.30 | 0.19 | 0.34 | 0.23 | 0.42 | 0.37 | 0.43 | 0.38 | 0.43 | 0.40 |

ATEC | 0.61 | N.A | 0.63 | N.A | 0.63 | N.A | 0.62 | N.A | 0.61 | N.A |

MPM | 0.7 | 0.55 | 0.7 | 0.625 | 0.7 | 0.675 | 0.65 | 0.675 | 0.65 | 0.675 |

VVD | N.A | 0.003 | N.A | 0.003 | N.A | 0.003 | N.A | 0.003 | N.A | 0.003 |

HEM | 0.67 | 0.55 | 0.675 | 0.6 | 0.67 | 0.61 | 0.61 | 0.56 | 0.58 | 0.56 |

signal and Noise value. Logically, the reference terms related Noise Margin analysis are described as below (Ref.

・ V_{OH}: (Voltage Output High Value). V_{OH} = Vdd because when the input voltage drops below V_{TH} of the inverter, no current flows. No current flow in turn means no voltage drop across the load resistor and V_{OUT} = V_{dd} = V_{OH}.

・ V_{OL}: (Voltage Output Low Value). If the input is driven to V_{OL} = V_{dd}, then the driver NMOS transistor is “ON” and since (V_{gs} − V_{t}) > V_{ds}, it is operating in linear mode. The V_{OUT} will be at V_{OL} and the V_{IN} will be at V_{OH}.

・ V_{IH}: (Voltage Input High Value). When V_{IN} = V_{IH}, the output is at V_{OL} and the NMOS is in the linear region.

・ V_{IL}: (Voltage Input Low Value). To determine noise margin we need V_{IL} which is one of two points where we have unity gain. When input low, output high and NMOS in saturation.

Considering the output characteristics of a resistive load inverter; the threshold voltage of the NMOS (V_{TH}) plays a significant role in determining the shape of the voltage transfer characteristic (V_{TC}) of a resistive load inverter. The V_{TH} appears as a critical parameter in expressions for V_{OL}, V_{IL}, and V_{IH}. V_{OH} is determined primarily by the power

supply voltage V_{dd}. The adjustment of V_{OL} receives primarily attention than V_{IL}, V_{IH}. Larger V_{TH} results in smaller V_{OL} resulting in larger transition slope and higher voltage swing as it can be perceived through

Ideally, when input voltage is logic “1”, the output voltage is expected to be at logic “0”. Hence, V_{IH} is V_{dd}, and V_{OL} is 0 V as shown in _{IL} is 0 V, and V_{OH} is V_{dd}. Using the values, the Noise Margins for an ideal inverter could be defined as follows:

・ NM_{L} (Noise Margin Low)

・ NM_{H} (Noise Margin High)

Practically the situation is not identical. It is observed that due to number of secondary effects like voltage droop, ground bounce, internal resistances, practices, etc.; V_{OH} is slightly less than V_{dd} i.e._{OL} is slightly higher that V_{ss} i.e.

・ NM_{L} (Noise Margin Low)

・ NM_{H} (Noise Margin High)

Hence, if input voltage (V_{IN}) lies somewhere between V_{OL} and V_{IL}, it would be detected as logic “0”, and would result in an output which is acceptable. Similarly, if input voltage (V_{IN}) lies between V_{IH} and V_{OH}, it would be detected as logic “1” and would result in an output which is acceptable.

Application of the extraction methods were implemented to calculate the Noise Immunity and Noise Margins for Resistive Load Inverter using 10-nm test device with Load Resistance R_{L} = 100 Ω and V_{dd} = 1 V. Referring to

・ We observe that with the increase in the Threshold voltage extraction value, the NM_{H} decreases and NM_{L} increases. For an Ideal Inverter, Noise Margins should be equal. Using QEM method for V_{TH} extraction, we obtain the most optimistic results (NM_{H} ≈ NM_{L}) in this regards. (Ref.

・ Using “.OPTION IVTH” command accessible in SPICE extraction method for V_{TH} extraction, we obtain the maximum output voltage swing i.e. V_{OH} − V_{OL} for resistive load NMOS inverter (Ref.

・ In the well-designed inverter, the Threshold value of the circuit (V_{in} = V_{out}) is nearly equal to V_{dd}/2. We obtain the flawless results in this regards using CCM extraction method (Ref.

METHOD | V_{TH} | NM_{H} | NM_{L} | ∆Vout (V_{OH}-V_{OL}) | ∆NM |NM_{H}-NM_{L}| | V_{TH}(Inverter) (Vin = Vout) |
---|---|---|---|---|---|---|

CCM | 0.355 | 0.4325 | 0.3440 | 0.9687 | 0.0885 | 0.498 |

DDEM | 0.44 | 0.3475 | 0.4242 | 0.9638 | 0.0767 | 0.572 |

LEM | 0.683 | 0.1045 | 0.6364 | 0.9331 | 0.5319 | 0.779 |

QEM | 0.381 | 0.4065 | 0.3687 | 0.9674 | 0.0378 | 0.521 |

SDM | 0.675 | 0.1125 | 0.6303 | 0.935 | 0.5178 | 0.771 |

TDM | 0.559 | 0.2285 | 0.5329 | 0.9536 | 0.3044 | 0.675 |

GM | 0.59 | 0.1975 | 0.5602 | 0.9498 | 0.3627 | 0.701 |

TCRM | 0.65 | 0.1375 | 0.6106 | 0.9403 | 0.4731 | 0.751 |

TM | 0.645 | 0.1425 | 0.6066 | 0.9412 | 0.4641 | 0.746 |

NMID | 0.625 | 0.1625 | 0.5900 | 0.9447 | 0.4275 | 0.73 |

NRHM | 0.625 | 0.1625 | 0.5900 | 0.9447 | 0.4275 | 0.73 |

RHM | 0.675 | 0.1125 | 0.6303 | 0.935 | 0.5178 | 0.771 |

SPICE | 0.30 | 0.4875 | 0.2915 | 0.9712 | 0.196 | 0.449 |

ATEC | 0.61 | 0.1775 | 0.5774 | 0.947 | 0.3999 | 0.718 |

MPM | 0.7 | 0.0875 | 0.6489 | 0.9286 | 0.5614 | 0.793 |

HEM | 0.67 | 0.1175 | 0.6265 | 0.9362 | 0.509 | 0.767 |

・ The slope of the output curve within the transition region describes the propagation delay properties of the circuit. The variation in the V_{TH} had a negligible effect on the slope of the curve resulting in nearly persistent switching characteristics for most of the extraction methods.

We presented, reviewed and critically compared several extraction methods currently used to determine the threshold voltage of bulk driven MOSFETs at 10-nm technology node and other various sub 45-nm technology nodes for precise evaluation of the respective method. The relative performance of all the methods was illustrated and compared under similar conditions by applying them to the test devices: bulk driven nano-MOSFETs with 10-nm technology node along with other various sub 45-nm technology nodes. We can perceive that the extracted threshold voltage largely depends on the method used for extraction specifically at nano-scale. The CCM has an ambiguous definition on the critical drain current (I_{D0}) contingent on technology being used. The LEM, QEM and TM outcomes are affected by extrinsic resistance effects, mobility degradation, Short Channel Effects and other second order present effects. SD, TD, GM, RH and TCRM are also widely affected by noise and are also not based on ideal threshold voltage definition condition. The MP is seldom used as 5% deviation value gives an ambiguous definition of threshold. The VVD extraction method is considerably ineffective at nano-meter technology node. In NMID and NRH, the correct calculation of maxima in wide ranges makes the extraction task much more difficult. We can also infer number of facts and properties from noise margin analysis performed using various threshold extraction methods. QEM provides the most optimistic balanced noise margin results. The maximum output voltage swing was observed using SPICE extraction method. CCM delivers the most appropriate results in calculating Threshold value of the circuit. The above listed features and properties of various extraction methods can be helpful in merging the threshold voltage compact models at nano-level technology nodes.

Swami, Y. and Rai, S. (2016) Comparative Methodical Assessment of Established MOSFET Threshold Voltage Extraction Methods at 10-nm Technology Node. Circuits and Systems, 7, 4248- 4279. http://dx.doi.org/10.4236/cs.2016.713349