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A new Single-Resistance-Controlled (SRC) sinusoidal oscillator using single Voltage Differencing-Differential Input Buffered Amplifier (VD-DIBA), only four passive components (two capacitors and two resistors), is presented. The proposed structure provides the following advantageous features: 1) independent control of oscillation frequency and condition of oscillation and 2) low active and passive sensitivities. The effects of non-idealities of the VD-DIBA on the proposed oscillator have also been investigated. The proposed SRC sinusoidal oscillator has been checked for robustness using Monte-Carlo simulation. SPICE simulation results have been included using 0.35 μm MIETEC technology to confirm the validity of the proposed SRC sinusoidal oscillator.

Numerous applications in control systems, signal processing, communications and instrumentation-measurement have been reported [

The applications, advantages and usefulness of VD-DIBA have now been recognized in the technical literature. Biolek and Biolkova [

The circuit symbol and equivalent circuit model of the VD-DIBA are shown in

The circuit analysis of proposed structure shown in

CE:

From Equation (2), the CO and FO can be given by:

CO:

FO:

Therefore, the CO is electronically controllable independently by g_{m} while FO is independently controlled by resistor R_{2}.

Assuming, Z-terminal of the VD-DIBA have

CE:

CO:

FO:

The left hand side of Equation (3) with the component values shown in this section turns out to be −0.060477 which is in accordance with Equation (3) (<0). On the other hand, the left hand side of Equation (6) using the components and parasitic values turns out to be −2.2588. It is, therefore, seen that both values are negative and satisfy the Equation (3) and Equation (6).

The active and passive sensitivities can be calculated as:

In the ideal case, the various sensitivities of _{1}, R_{2}, C_{1}, C_{2}, C_{z} and R_{z} are found to be

Considering the typical values of various parasitic e.g. C_{z} = 0.81 pF, R_{z} = 53 kΩ, β^{+} = β^{−} = 1 along with C_{1} = C_{2} = 100 pF, R_{1} = R_{2} = 8 kΩ, the various sensitivities are found to be

The proposed SRC sinusoidal oscillator is simulated using CMOS VD-DIBA (as shown in _{1} = C_{2} = 100 pF, R_{1} = R_{2} = 8 kΩ. The transconductance of VD-DIBA was controlled by bias voltage V_{B}_{1}. The transient response of the proposed SRCO showing the buildup of oscillations for above component values is shown in

waveform generated by the oscillator for the frequency 203.01 kHz (for the same component values) is shown in _{1}, the value of oscillation frequency remains close to its normal value of 204.459 kHz and hence almost unaffected by change in R_{1}.

of the frequency with resistance R_{2} varied from 5 kΩ to 25 kΩ. These results, thus, confirm the validity of the proposed structure. A comparison with other previously known SRCOs using different active building blocks has been given in

The CMOS VD-DIBA is implemented using 0.35 µm MIETEC technology. The various transistor model parameters used are listed in

A new application of VD-DIBA has been proposed in the realization of SRCO. The proposed structure employs a minimum possible number of passive elements (namely,

Reference | Active Component(s) | Grounded Capacitors | Floating Capacitors | Resistors | CO and FO Independently Controllable |
---|---|---|---|---|---|

[ | 1 | 1 | 1 | 3 | YES |

[ | 2 | 2 | 0 | 3 | YES |

[ | 1 | 1 | 1 | 3 | YES |

[ | 1 | 1 | 1 | 3 | YES |

[ | 2 | 2 | 0 | 3 | YES |

[ | 1 | 2 | 0 | 4 | NO |

[ | 1 | 2 | 0 | 3/2 | YES |

[ | 1 | 2 | 0 | 3 | YES |

[ | 1 | 1 (virtually grounded) | 1 | 3 | YES (only in second topology of |

[ | 1 | 1 (virtually grounded) | 1 | 3 | NO |

[ | 1 | 2 | 0 | 2 | YES |

[ | 1 | 1 | 1 | 2 | YES |

[ | 1 | 2 | 0 | 2 | YES |

[ | 3 | 2 | 0 | 0 | YES |

[ | 2 | 2 | 0 | 1 | YES |

[ | 2 | 2 | 0 | 2 | YES (fully uncoupled) |

Proposed | 1 | 1 | 1 | 2 | YES |

.MODEL N NMOS (LEVEL = 3 TOX = 7.9E-9 NSUB = 1E17 GAMMA = 0.5827871 PHI = 0.7 VTO = 0.5445549 DELTA = 0 UO = 436.256147 ETA = 0 THETA = 0.1749684 KP = 2.055786E-4 VMAX = 8.309444E4 KAPPA = 0.2574081 RSH = 0.0559398 NFS = 1E12 TPG = 1 XJ = 3E-7 LD = 3.162278E-11 WD = 7.046724E-8 CGDO = 2.82E-10 CGSO = 2.82E-10 CGBO = 1E-10 CJ = 1E-3 PB = 0.9758533 MJ = 0.3448504 CJSW = 3.777852E-10 MJSW = 0.3508721) |
---|

.MODEL P PMOS (LEVEL = 3 TOX = 7.9E-9 NSUB = 1E17 GAMMA = 0.4083894 PHI = 0.7 VTO = −0.7140674 DELTA = 0 UO = 212.2319801 ETA = 9.999762E-4 THETA = 0.2020774 KP = 6.733755E-5 VMAX = 1.181551E5 KAPPA = 1.5 RSH = 30.0712458 NFS = 1E12 TPG = −1 XJ = 2E-7 LD = 5.000001E-13 WD = 1.249872E-7 CGDO = 3.09E-10 CGSO = 3.09E-10 CGBO = 1E-10 CJ = 1.419508E-3 PB = 0.8152753 MJ = 0.5 CJSW = 4.813504E-10 MJSW = 0.5) |

Transistor | W/L (µm) |
---|---|

M1-M6 | 14/1 |

M7-M9 | 14/0.35 |

M10-M18 | 4/1 |

M19-M22 | 7/0.35 |

two resistors and two capacitors) and offers independent control of FO through the resistor R_{2} and CO through the transconductance g_{m}. The proposed structure has low active and passive sensitivities._{ }The robustness of the proposed SRCO circuit has been confirmed by the Monte-Carlo analysis. The workability of proposed structure has been confirmed by SPICE simulation with 0.35 µm MIETEC technology. However, any SRCO employing single VD-DIBA with both grounded capacitors and offering independent electronic control of FO is open to investigation.

Pushkar, K.L., Goel, R.K., Gupta, K., Vivek, P. and Ashraf, J. (2016) New VD-DIBA-Based Single-Resis- tance-Controlled Sinusoidal Oscillator. Circuits and Systems, 7, 4145-4153. http://dx.doi.org/10.4236/cs.2016.713341