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This paper presents area efficient architecture of modulo 2
^{n }- 3 adder. Modulo adder is one of the main components for the implementation of residue number system (RNS) based applications. The proposed modulo 2
^{n }
- 3 adder is implemented effectively, which utilizes parallel prefix and sparse concepts. The carries of some bits are calculated with the help of sparse approach in log
_{2}n prefix levels. This scheme is implemented with the help of idempotency property of the parallel prefix carry operator and its consistency. Parallel prefix structure contributes to fast carry computation. This will reduce area as well as routing complexity efficiently. The presented adder has double representation of residues in {0, 1, and 2}. The proposed adder offers significant reduction in area as the number of bits increases.

Residue number system (RNS) is a classical and a non weighted number system [

An RNS is specified by set of moduli_{k}. The dynamic range is denoted by M, which is defined as a product of moduli set [^{n} − 1 modulo addition. H. T. Vergos et al. [^{n} + 1 addition. The design offers reduction in cell area, wiring complexity and power consumption in conjunction with high speed of operation with the concept of sparse modulo 2^{n} + 1 adder which is based on the extension of eminent idempotency property of prefix operator. Latency compatible parallel prefix modulo 2^{n} − 3 adder is presented in [

Double representation for modulo (2^{n} − 3) i.e. (0, 1, and 2) is explained in [^{n} − 3 adder which uses the concept of parallel prefix sparse adder. Parallel prefix approach has better compatibility with modulo (2^{n} − 1). Sparse parallel prefix adder is endorsed for large word-lengths addition, curtails the wiring and area design without affecting the delay. The proposed adder has lesser area as compared to existing modulo 2^{n} − 3 adder [

This paper is organized as follows: Section 2 describes basics of parallel prefix addition. In Section 3, modulo 2^{n} − 3 adder is discussed. Section 4 explains about sparse concept for modulo 2^{n} − 3 adder. Finally, unit gate area and unit gate delay are calculated in Section 5.

Parallel-Prefix adder (PPA) performs parallel addition which plays a key role in microprocessors, DSP, mobile devices and other high speed applications. Parallel-Prefix structure reduces logic complexity and delay thereby enhancing the performance in term of area and power dissipation. Let the two inputs are A, B described as _{i}), propagation (P_{i}) and half sum (H_{i}) bits given as.

where

(2)

(3)

The equations that are useful for generation of carry network [

Or

(5)

In the above expression

The third stage is an “xor” operation of half sum bits and previous carry to get the final sum.

For the design of large word length adders the concept of sparse is used [^{th} bit therefore it is called sparse-k parallel prefix adder.

The generalized formula for modulo 2^{n} − 3 adder is described as [

The above expression for modulo 2^{n} − 3 adder has double representation for {0, 1 and 2} with the last three numbers that are 2^{n} − 3, 2^{n} − 2, 2^{n} − 1.

Unlike the modulo 2^{n} − 1 adder, here we have to add the end around carry to the position 0 as well as position 1, this creates problem in implementation of the modulo PPA structure during addition. The two inputs and the EAC for position zero and position one [

Where

output of

The alternative approach has been presented for modulo adder using PPA structures [^{th} carry expression in the case of modulo 2^{n} − 3 adder is as follows:

where,

The sum expression for bit position one is

From above expression, the carries can be calculated by propagate and generate bits. _{1} is implemented with the help of multiplexer taking

The delay offered by RPP adder structure is more as compared to TPP adder structure due to extra prefix level. The TPP structure has a disadvantage of routing complexity as well as excessive area problem as the bit length of adder increases.

In this segment, we proposed modulo 2^{n} − 3 adder by utilizing the concept of integer

sparse-4 PPA in which the same carry select adder, used to implement sparse modulo 2^{n} − 3 adder. In sparse-4, the carry is generated for every 4^{th} bit. We are using carry select adder for modulo operation so we are required to show that the rest of carries are associated with available ones.

From the general carry expression given in Equation (8)

Let n = 32 bit, the carry expression

We can also write it as:

(12)

This can also be expanded as:

(13)

By the formula of Rearraging the redundant terms given in [

(14)

Finally it is expressed by,

(15)

So

(16)

At last, the carry expression

From above expression we conclude that this relation is quite similar to integer adder. Therefore we can directly use carry select block ^{n} − 3 adder, it is based on carry

_{1}. The ^{n} − 3 adder. The remaining bits uses carry select block of ^{n} − 3) adder.

This sparse-4 modulo 2^{n} − 3 adder has double representation for {0,1,2} with 2^{n} − 3, 2^{n} − 2, 2^{n} − 1, so there are six pairs of combinations in which two pairs has tendency to produce wrong addition result. The solution for this problem is explained in [

^{n} − 3 Adder having lesser area than previously reported modulo adder.

The theoretical area and delay analysis is explained in terms of area (∆a) and delay (∆g) of basic 2-input gates. From the concept of unit gate model, basic 2-input AND, OR, NAND, NOR are assumed as single unit gate (∆a, ∆g), whereas exclusive-OR & exclusive-NOR and assumed to be double unit gate (2∆a, 2∆g) [

The delay offered by proposed sparse modulo 2^{n} − 3 adder is same as [

The percentage reduction in area increases as the number of bit length increases. We have also elaborated proposed work with HDL code written on Xilinx 14.7 and verified for correctness using simulation tests. Number of lookup table (LUTs) count is given in

In this paper, we have proposed an area efficient sparse modulo 2^{n} − 3 adder which plays an important role in verity of computer applications. The efficiency in term of area of proposed adder is explained by using the concept of unit gate model. For different value of n (=8, 16, 32, 64), the percentage area reduction is (=2.3, 13.2, 21, 27.54)

Adder | Delay (∆g) | Area (∆a) |
---|---|---|

[ | ||

Proposed |

Bits (n) | [ | Proposed | Reduction % | |||
---|---|---|---|---|---|---|

Delay (∆g) | Area (∆a) | Delay (∆g) | Area (∆a) | Delay (∆g) | Area (∆a) | |

8 16 32 64 | 10 12 14 16 | 126 310 726 1654 | 10 12 14 16 | 123 269 573 1205 | 0 0 0 0 | 2.3 13.2 21.0 27.54 |

[ | Proposed Sparse Adder | % Reduction in LUT Count |
---|---|---|

64 | 42 | 34 |

respectively with same delay. Simulation results show that the area of proposed adder has been reduced by 34% in term of LUT count for n = 8. Therefore, it is observed that, the presented modulo adder offers less area in performing the addition for larger word length input and also reduces the routing complexity in comparison with the previously reported adder.

Jaiswal, R.K., Kumar, C.N. and Mishra, R.A. (2016) Area Ef- ficient Sparse Modulo 2^{n} − 3 Adder. Circuits and Systems, 7, 4024-4035. http://dx.doi.org/10.4236/cs.2016.712333