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In this, today ’ s world immeasurable analysis goes within the field of communication and signal processing applications. The FIR filter is mostly employed in filtering applications to enhance the quality of the signal. In any processor, the performance of the system is based on the speed of the multiplier unit involved in its operation. Since multiplier forms the indispensable building blocks of the FIR filter system. Its performance has contributed in determining the execution of the FIR filter system. Also, due to the tremendous development in the technology , many approaches such as an array, Vedic methods are made to speed up the multiplier computations. The problem in speed - up operation and resource utilization of hardware with all the conventional methods due to the critical path found in partial products has to be optimized using proposed method. This paper presents the implementation and execution of a FIR Filter design using Anurupye multiplier. Here the FIR filter is examined by using various multiplier algorithms such as Anurupye, Urdhava Tiryagbhyam, and array multipliers. The FIR filter is simulated for analyzing delay ; area and power are meted out and lessened by utilizing proposed Anurupye multiplier. The FIR filter design utilizing proposed multiplier offers delay around 18.99 and only 4% of LUT slice utilization compared to existing methods. This architecture is coded in VHDL, simulated using the ModelSim and synthesize d with Xilinx.

In overall DSP applications [

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In this paper, we present a high-speed efficient multiplier for the FIR Filter on ancient Vedic mathematic formulae. So we process with Anurupye Vedic multiplier methods for computing discrete linear convolution. The proposed Anyrupye Vedic algorithm is analyzed with other conventional algorithms in terms of power, delay, and the area is found to be much efficient. Anurupye denotes “proportionality” consisting of both working and theoretical index (base) very suitable for values far away from the index which was not possible in other techniques. These calculated outcomes are considered for power, delay, and area using a Vedic algorithm such as Anurupye and Urdhava Triyakbhayam along with array multiplier. The Vedic algorithm Anurupye is found to be fast and effective. This method is implemented in FIR design methodology for enhancing filtering functions in eliminating unwanted noise. Thereby the system efficiency with fewer resources and lesser computation is improved.

The former practices were recalled from Indian Sanskrit works named as the Vedas, concerning 1911 in addition to 1918 by Sri Bharati Krishna Tirthaji and from (1884- 1960) the Atharva Vedas. As indicated by his investigation, the greater part of the arithmetic is found with sixteen sutras, or word-formula [

This method is a technique in Vedic mathematics to increase the speed and area parameters of a multiplier utilized. Hence this algorithm is used to produce a partial product with its summation assessed concurrently to produce a net result. This process is the greatest asset of this method. The major advantage of this multiplier with other multipliers is its uniformity of computation. This flexible nature leads to the layout design with a simple and realistic approach employed to several forms of multiplications. In a Sanskrit the term Urdhva implies vertical up-down, Tiryakbhyam implies left to right or the other way around [

Today we are discussing a genuine significant sutra [

Since both the numbers are far from 10 we consider 30 as our working index.

STEP 1: Register the compliments from the working index adjacent to the given number.

10 × 3 = 30

32 +2

36 +6

STEP 2: Right Hand Side (RHS)

10 × 3 = 30

32 +2

36 +6

38 /+12

Cross adds diagonally to get 38. Multiply with its compliments (+6) × (+2) = 12 to get R.H.S.

Since we have 10 as our working index only one digit (2) is considered. Another digit (1) is propagated as carry to L.S.B.

STEP 3: Left Hand Side (LHS)

10 × 3 = 30

32 +2

36 +6

115 /12

The L.H.S is obtained by taking a product with its corresponding working index.

38 × 3 = 114. Then taking the sum of the L.H.S with carry 114 + 1 (carry) = 115.

Thus the answer is obtained from the above calculations as 32 × 36 = 1152.

A FIR filter is also known as the non-recursive digital filter. In this filter, no feedback exists and the output depends only on the present and the past input values of the signal [

The output equation for the FIR filter [

where, k(n) is the input, g(n) is the output of the given signal to the FIR filter respectively, j(n) is the impulse response (i.e.) the filter coefficients. Linear phase FIR filters are used in the application such as audio and video where exact linear phase response is required [

In this approach, we design a FIR filter by implementing a proposed Anurupye multiplier algorithm. The conventional direct form structure with 8-Tap FIR filter is shown in the

The design of the Anurupye Vedic multiplier has been analyzed and this algorithm is utilized in FIR Filter for prevailing low power and high performance. This proposed method is coded in Hardware description language such as VHDL, simulated using Model Sim-Altera 6.3 g and the net synthesize is obtained in the Xilinx ISE14.4 Software.

The Design of 8 × 8 multiplier topologies for various multipliers such as Array multiplier, Vedic multipliers such as Urdhava Triyagbhyam and Anurupye algorithm are shown in

The analysis is examined for different multiplier unit. From the comparison, the memory usage of Anurupye is 191 mb small compared to other multiplier architecture. Anurupye Vedic multiplier entertains the greatest improvements compared to other

Multipliers | Memory | Power | Delay | |
---|---|---|---|---|

Array | 196 mb | 56 mW | 22.05 ns | |

Vedic | Urdhava Triyagbhyam | 194 mb | 52 mW | 23 ns |

Anurupye | 191 mb | 34 mW | 20.54 ns |

multipliers over combinational path delay and the orderliness of arrangements. The Delay in proposed multiplier for 8 × 8-bit number is 20.54 ns whereas the delays in Urdhava Triyagbhyam and Array are and 22.0 ns and 23 ns respectively. Thus, this multiplier shows the maximum speed among conventional multipliers. This benefits than others provide the choice to prefer the best multiplier. It has less number of gates required for given 8 × 8 bit multiplier, so its power dissipation is 34 mW very lesser and it has less switching activity as associated to array multiplier. Figures 4-6 show the graph for the multiplier comparison based on memory consumption, delay and power consumption.

The logical simulation of recommended multiplier architecture is simulated and the result is shown in

Multiplier | Power (mW) | Delay (ns) | No of slices | Memory (Mb) |
---|---|---|---|---|

Anurupye Multiplier | 34 | 20.54 | 132 | 191 |

FIR Implementation | 14 | 18.99 | 120 | 109 |

implemented with lesser no of slices, memory, power, and delay. The RTL view of the FIR filter is shown in

In this paper, we have bestowed a unique approach to improve the performance of the FIR Filter considerably by using an Anurupye Vedic Multiplier. This proposed multiplier provides improved performance parameters with less number of gates used for a given 8 × 8 bit multiplier. Also, from the results achieved it can be obviously apparent that the delay of this multiplier is relatively reduced compared to the other common designs of multipliers. It’s therefore, decided that the Anurupye Vedic Multiplier based FIR filter design would be a good choice for high-speed DSP applications in the future. Further research can be performed with the other algorithms of Vedic mathematics and to obtain efficient design to be utilized in cryptography network for providing secure data transfer.